Apparatus and method for efficient graphics processing including ray tracing

Patent metadata

Field	Value
Publication number	US-12536732-B2
Application number	US-202418675746-A
Country	US
Kind code	B2
Filing date	May 28, 2024
Priority date	Aug 17, 2020
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.

First claim

What is claimed is:

1 . A graphics processor comprising:
circuitry to schedule shaders for execution; and execution hardware logic coupled to the circuitry to execute the shaders using a plurality of fixed sized blocks of memory, a functional unit of the execution hardware logic to request a write access with a hash identifier (ID) that is mapped to a portion of the plurality of fixed sized blocks of memory in executing a first shader, wherein the first shader is to write content to the portion of the plurality of fixed sized blocks of memory, and wherein a second shader is to request a read access with the hash ID to read the content from the portion of the plurality of fixed sized blocks of memory.

2 . The graphics processor of claim 1 , wherein the hash ID is generated based on one or more of a ray tracing instance ID, a geometry ID, and a frame counter.

3 . The graphics processor of claim 1 , wherein the first shader is to lock the portion of the plurality of fixed sized blocks of memory during writing the content to the portion of the plurality of fixed sized blocks of memory.

4 . The graphics processor of claim 1 , wherein responsive to the portion of the plurality of fixed sized blocks of memory identified by the hash ID not existing, a new portion of the plurality of fixed sized blocks of memory is allocated and associated with the hash ID.

5 . The graphics processor of claim 4 , wherein a flag is set for the new portion of the plurality of fixed sized blocks of memory to indicate that the new portion of the plurality of fixed sized blocks of memory is available for allocating.

6 . The graphics processor of claim 4 , wherein upon no new portion of the plurality of fixed sized blocks of memory being found, an existing portion of the plurality of fixed sized blocks of memory is evicted and reallocated as the new portion of the plurality of fixed sized blocks of memory associated with the hash ID.

7 . The graphics processor of claim 6 , wherein evicting the existing portion of the plurality of fixed sized blocks of memory follows a least recently used (LRU) eviction policy and the existing portion of the plurality of fixed sized blocks of memory is used least recently.

8 . The graphics processor of claim 1 , wherein upon a new portion of the plurality of fixed sized blocks of memory being allocated, the execution hardware logic is to execute a user compute shader, the user compute shader to write triangles in the portion of the plurality of fixed sized blocks of memory.

9 . The graphics processor of claim 1 , wherein the read access with the hash ID from the second shader is blocked until the write access with the hash ID in executing the first shader is fulfilled.

10 . The graphics processor of claim 1 , wherein the plurality of fixed sized blocks of memory comprises a memory buffer subdivided into tiles.

11 . A method comprising:
scheduling shaders for execution; executing the shaders by execution hardware logic using a plurality of fixed sized blocks of memory; requesting a write access with a hash identifier (ID) that is mapped to a portion of the plurality of fixed sized blocks of memory in executing a first shader; writing, by the first shader, content to the portion of the plurality of fixed sized blocks of memory; and requesting, by a second shader, a read access with the hash ID to read the content from the portion of the plurality of fixed sized blocks of memory.

12 . The method of claim 11 , wherein the hash ID is generated based on one or more of a ray tracing instance ID, a geometry ID, and a frame counter.

13 . The method of claim 11 , wherein the first shader lacks-lock the portion of the plurality of fixed sized blocks of memory during writing the content to the portion of the plurality of fixed sized blocks of memory.

14 . The method of claim 11 , wherein responsive to the portion of the plurality of fixed sized blocks of memory identified by the hash ID not existing, a new portion of the plurality of fixed sized blocks of memory is allocated and associated with the hash ID.

15 . The method of claim 11 , wherein the read access with the hash ID from the second shader is blocked until the write access with the hash ID in executing the first shader is fulfilled.

16 . The method of claim 11 , wherein the plurality of fixed sized blocks of memory comprises a memory buffer subdivided into tiles.

17 . A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform:
scheduling shaders for execution; executing the shaders by execution hardware logic using a plurality of fixed sized blocks of memory; requesting a write access with a hash identifier (ID) that is mapped to a portion of the plurality of fixed sized blocks of memory in executing a first shader; writing, by the first shader, content to the portion of the plurality of fixed sized blocks of memory; and requesting, by a second shader, a read access with the hash ID to read the content from the portion of the plurality of fixed sized blocks of memory.

18 . The non-transitory machine-readable medium of claim 17 , wherein the hash ID is generated based on one or more of a ray tracing instance ID, a geometry ID, and a frame counter.

19 . The non-transitory machine-readable medium of claim 17 , wherein the first shader locks the portion of the plurality of fixed sized blocks of memory during writing the content to the portion of the plurality of fixed sized blocks of memory.

20 . The non-transitory machine-readable medium of claim 17 , wherein responsive to the portion of the plurality of fixed sized blocks of memory identified by the hash ID not existing, a new portion of the plurality of fixed sized blocks of memory is allocated and associated with the hash ID.

Assignees

• Intel Corp

Inventors

• Woop Sven
• Doyle Michael J
• Kothandaraman Sreenivas
• Vaidyanathan Karthik
• Appu Abhishek R
• Benthin Carsten
• Surti Prasoonkumar
• Gruen Holger
• Junkins Stephen
• Lake Adam
• Alfieri Bret G
• Liktor Gabor
• Barczak Joshua
• Lee Won-Jong

Classifications

• G06T2210/21

  Collision detection, intersection · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T1/60

  Memory management · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/06 Primary

  Ray-tracing · CPC title