Memristor and neuromorphic device

Patent metadata

Field	Value
Publication number	US-12536423-B2
Application number	US-202217865966-A
Country	US
Kind code	B2
Filing date	Jul 15, 2022
Priority date	Jul 15, 2022
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

A memristor includes a first variable conductance element and a second variable conductance element. A minimum value of conductance of the second variable conductance element during reading is larger than a maximum value of conductance of the first variable conductance element during reading. In the memristor, a first read path when the conductance of the first variable conductance element is read merges with a second read path when the conductance of the second variable conductance element is read.

First claim

What is claimed is:

1 . A memristor comprising:
a first variable conductance element; and a second variable conductance element, wherein a minimum value of conductance of the second variable conductance element during reading is larger than a maximum value of conductance of the first variable conductance element during reading, and wherein a first read path when the conductance of the first variable conductance element is read merges with a second read path when the conductance of the second variable conductance element is read.

2 . The memristor according to claim 1 , wherein the first read path and the second read path are connected in parallel.

3 . The memristor according to claim 1 , wherein a conductance change range for a gradation of the second variable conductance element is larger than a conductance change range for a gradation of the first variable conductance element.

4 . The memristor according to claim 3 , wherein the conductance change range for a gradation of the second variable conductance element is larger than a maximum change range of the conductance of the first variable conductance element.

5 . The memristor according to claim 4 , wherein the conductance change range for a gradation of the second variable conductance element is less than or equal to a sum of the maximum change range of the conductance of the first variable conductance element and the conductance change range for a gradation of the first variable conductance element.

6 . The memristor according to claim 1 , wherein a lowest resistivity of the first variable conductance element is greater than a lowest resistivity of the second variable conductance element.

7 . The memristor according to claim 1 , wherein an area occupied by the first variable conductance element when viewed from above in a lamination direction is smaller than an area occupied by the second variable conductance element when viewed from above in the lamination direction.

8 . The memristor according to claim 1 , further comprising:
a first switching element connected to the first variable conductance element and configured to control a write current for the first variable conductance element; and a second switching element connected to the second variable conductance element and configured to control a write current for the second variable conductance element, wherein an area of the first switching element is smaller than an area of the second switching element when viewed from above in a lamination direction.

9 . The memristor according to claim 1 , wherein the first variable conductance element and the second variable conductance element are at different height positions in a lamination direction.

10 . The memristor according to claim 1 , wherein the number of gradations of the second variable conductance element is larger than the number of gradations of the first variable conductance element.

11 . The memristor according to claim 1 , wherein the number of gradations of the second variable conductance element is smaller than the number of gradations of the first variable conductance element.

12 . The memristor according to claim 1 ,
wherein the first variable conductance element includes
a first reference layer;
a first magnetic recording layer;
a first nonmagnetic layer between the first reference layer and the first magnetic recording layer;
a first electrode electrically connected to the first magnetic recording layer; and
a second electrode separated from the first electrode and electrically connected to the first magnetic recording layer, and
wherein the second variable conductance element includes
a second reference layer;
a second magnetic recording layer;
a second nonmagnetic layer between the second reference layer and the second magnetic recording layer;
a third electrode electrically connected to the second magnetic recording layer; and
a fourth electrode separated from the third electrode and electrically connected to the second magnetic recording layer.

13 . The memristor according to claim 12 , wherein a length of the first magnetic recording layer in a first width direction perpendicular to a line segment connecting the first electrode and the second electrode along the first magnetic recording layer is shorter than a length of the second magnetic recording layer in a second width direction perpendicular to a line segment connecting the third electrode and the fourth electrode along the second magnetic recording layer.

14 . The memristor according to claim 12 , further comprising a shared read electrode,
wherein the shared read electrode is connected to the first reference layer and the second reference layer.

15 . The memristor according to claim 14 , wherein the second electrode and the fourth electrode are connected and integrated.

16 . The memristor according to claim 15 , wherein a read current flows between the shared read electrode and the second electrode and between the shared read electrode and the fourth electrode.

17 . The memristor according to claim 14 , comprising:
a first pair element including the first variable conductance element and the second variable conductance element; and a second pair element including a third variable conductance element identical to the first variable conductance element and a fourth variable conductance element identical to the second variable conductance element, wherein the first variable conductance element, the second variable conductance element, the third variable conductance element, and the fourth variable conductance element are connected to the same shared read electrode, wherein when a read current flows from the first reference layer to the first magnetic recording layer in the first variable conductance element and a read current flows from the second reference layer to the second magnetic recording layer in the second variable conductance element, a read current flows from the first magnetic recording layer to the first reference layer in the third variable conductance element and a read current flows from the second magnetic recording layer to the second reference layer in the fourth variable conductance element, and wherein when a read current flows from the first magnetic recording layer to the first reference layer in the first variable conductance element and a read current flows from the second magnetic recording layer to the second reference layer in the second variable conductance element, a read current flows from the first reference layer to the first magnetic recording layer in the third variable conductance element and a read current flows from the second reference layer to the second magnetic recording layer in the fourth variable conductance element.

18 . A memristor comprising:
a first variable conductance element; and a second variable conductance element, wherein a minimum value of conductance of the second variable conductance element during reading is larger than a maximum value of conductance of the first variable conductance element during reading, and wherein the memristor sums the conductance of the first variable conductance element and the conductance of the second variable conductance element.

19 . A neuromorphic device comprising:
a plurality of memristors; and a control device configured to control the plurality of memristors, wherein each of the plurality of memristors is the memristor according to claim 1 , wherein the control device configured to change only the conductance of the second variabl

Assignees

• Tdk Corp

Inventors

• Yamada Shogo
• SUDA Keita
• Terasaki Yukio
• Sasaki Tomoyuki

Classifications

• H10N50/80

  Constructional details · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title