Boundary cell having a common semiconductor type for library cell

Patent metadata

Field	Value
Publication number	US-12536360-B2
Application number	US-202217873015-A
Country	US
Kind code	B2
Filing date	Jul 25, 2022
Priority date	Jul 26, 2021
Publication date	Jan 27, 2026
Grant date	Jan 27, 2026

Abstract

Boundary cells are used to abut two standard cell blocks. A standard cell block for an integrated circuit device includes a first standard cell, and a first boundary cell disposed adjacent to the first standard cell and along a boundary of the standard cell block. The first boundary cell includes a first region, a first dummy region, and a first layer extension region. The first region is abutted with the first standard cell and the first dummy region. The first dummy region is abutted with the first layer extension region. The first region and the first dummy region each include one or more non-functional layers. The first region, the first dummy region, and the first layer extension region are of a first semiconductor type.

First claim

What is claimed is:

1 . A standard cell block for an integrated circuit device, the standard cell block comprising:
standard cells interconnected to perform one or more functions of the standard cell block; and boundary cells disposed adjacent to the standard cells and along a boundary and an outer edge of the standard cells, the boundary cells comprising a first boundary cell comprising:
a first region, a first dummy region, and a first layer extension region, the first region abutted with a first standard cell of the standard cells and the first dummy region, and the first dummy region is abutted with the first layer extension region, wherein the first region and the first dummy region each include one or more non-functional layers, wherein the first region, the first dummy region, and the first layer extension region are of a first semiconductor type, wherein the first region and the first dummy region overlap a second layer extension region of a second boundary cell of boundary cells of a second standard cell block, and the first layer extension region overlaps a second region and a second dummy region of the second boundary cell, and wherein two or more of the boundary cells are disposed adjacent to each other along the boundary and the outer edge.

2 . The standard cell block of claim 1 , wherein the first semiconductor type is a p-type or an n-type.

3 . The standard cell block of claim 1 , wherein a first placement and routing boundary is between the first layer extension region and the first dummy region.

4 . The standard cell block of claim 3 , wherein the first placement and routing boundary is aligned with a second placement and routing boundary of the second standard cell block.

5 . The standard cell block of claim 4 , wherein the second region, the second dummy region, and a second layer extension region of the second standard cell block are of the first semiconductor type.

6 . The standard cell block of claim 4 , wherein a height of the first layer extension region is greater than a height of the first region and a height of the first dummy region.

7 . The standard cell block of claim 1 , wherein the first standard cell comprises a power supply line routed in a third region of the first semiconductor type, wherein the first region is abutted with the third region.

8 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
provide a first standard cell block, the first standard cell block comprising:
standard cells of a standard cell library based on a circuit design, the standard cells interconnected to perform one or more functions of the first standard cell block; and
boundary cells disposed adjacent to the standard cells and along a boundary and an outer edge of the standard cells, the boundary cells comprising a first boundary cell comprising:
a first region, a first dummy region, and a first layer extension region, the first region abutted with a first standard cell of the standard cells and the first dummy region, and the first dummy region is abutted with the first layer extension region, wherein the first region and the first dummy region each include one or more non-functional layers, wherein the first region, the first dummy region, and the first layer extension region are of a first semiconductor type, wherein the first region and the first dummy region overlap a second layer extension region of a second boundary cell of boundary cells of a second standard cell block, and the first layer extension region overlaps a second region and a second dummy region of the second boundary cell, and wherein two or more of the boundary cells are disposed adjacent to each other along the boundary and the outer edge.

9 . The non-transitory computer readable medium of claim 8 , wherein the first semiconductor type is a p-type or an n-type.

10 . The non-transitory computer readable medium of claim 8 , wherein a first placement and routing boundary is between the first layer extension region and the first dummy region.

11 . The non-transitory computer readable medium of claim 10 , the first placement and routing boundary is aligned with a second placement and routing boundary of the second standard cell block.

12 . The non-transitory computer readable medium of claim 11 , wherein the second region, the second dummy region, and a second layer extension region of the second standard cell block are of the first semiconductor type.

13 . The non-transitory computer readable medium of claim 8 , wherein a height of the first layer extension region is greater than a height of the first region and a height of the first dummy region.

14 . The non-transitory computer readable medium of claim 8 , wherein the first standard cell comprises a power supply line routed in a third region of the first semiconductor type, wherein the first region is abutted with the third region.

15 . A method comprising:
placing standard cells of a standard cell library within a first standard cell block of a plurality of standard cell blocks; and placing boundary cells along a boundary and an outer edge of the standard cells, the boundary cells comprising a first boundary cell comprising:
a first region abutting a second region of a first standard cell of the standard cells;
a first dummy region abutting the first region, each of the first dummy region and the first region include a non-functional layer and overlap a second layer extension region of a second boundary cell of boundary cells of a second standard cell block; and
a first layer extension region abutting the first dummy region, wherein the first region, the first dummy region, the first layer extension region, and the second region are of a first semiconductor type, the first layer extension region overlaps a third region and a second dummy region of the second boundary cell, and two or more of the boundary cells are disposed adjacent to each other along the boundary and the outer edge.

16 . The method of claim 15 , further comprising generating a gate level netlist by interconnecting the plurality of standard cell blocks.

17 . The method of claim 15 , wherein the first semiconductor type is a p-type or an n-type.

18 . The method of claim 15 , wherein a first placement and routing boundary is between the first layer extension region and the first dummy region.

19 . The method of claim 15 further comprising:
placing a second standard cell of the standard cell library within the second standard cell block of the plurality of standard cell blocks; and
placing the second boundary cell along a boundary of the second standard cell block, wherein:
the third region abuts a fourth region of the second standard cell;
the second dummy region abuts the third region; and
the second layer extension region abuts the second dummy region, wherein the third region, the second dummy region, the second layer extension region, and the fourth region are of the first semiconductor type.

20 . The method of claim 15 , wherein a first placement of the first standard cell block and routing boundary is aligned with a second placement and routing boundary of the second standard cell block.

Assignees

• Synopsys Inc

Inventors

• Jain Arpit

Classifications

• G06F30/3953

  detailed · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H10D89/10

  Integrated device layouts · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title