Light-emitting device, pixel circuit, light-emitting substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-12532580-B2
Application number	US-202117789351-A
Country	US
Kind code	B2
Filing date	May 31, 2021
Priority date	May 31, 2021
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

A light-emitting device includes a first semiconductor layer, a light-emitting functional layer and a second semiconductor layer that are stacked. The first semiconductor layer includes a first semiconductor pattern and a second semiconductor pattern. The light-emitting functional layer includes a first light-emitting pattern and a second light-emitting pattern spaced apart. The second semiconductor layer includes a third semiconductor pattern and a fourth semiconductor pattern spaced apart. Orthographic projections of the first semiconductor pattern, the first light-emitting pattern and the third semiconductor pattern on a reference plane at least partially overlap to form a first light-emitting portion. Orthographic projections of the second semiconductor pattern, the second light-emitting pattern and the fourth semiconductor pattern on the reference plane at least partially overlap to form a second light-emitting portion. The reference plane is parallel to a plane where the first semiconductor layer is located.

First claim

What is claimed is:

1 . A light-emitting device, comprising:
a first semiconductor layer including a first semiconductor pattern and a second semiconductor pattern; a light-emitting functional layer disposed on one of two opposite sides of the first semiconductor layer in a thickness direction of the first semiconductor layer, the light-emitting functional layer including a first light-emitting pattern and a second light-emitting pattern spaced apart; a second semiconductor layer disposed on a side of the light-emitting functional layer away from the first semiconductor layer, the second semiconductor layer including a third semiconductor pattern and a fourth semiconductor pattern spaced apart; an electrode layer disposed on a side of the second semiconductor layer away from the first semiconductor laver, the electrode layer including a first electrode and a second electrode spaced apart, wherein the first electrode is electrically connected to the third semiconductor pattern, and the second electrode is electrically connected the fourth semiconductor pattern; and a passivation layer disposed between the second semiconductor layer and the electrode layer, wherein the passivation layer is provided with a first via hole and a second via hole therein, the first electrode is electrically connected to the third semiconductor pattern through the first via hole, and the second electrode is electrically connected to the fourth semiconductor pattern through the second via hole; wherein, orthographic projections of the first semiconductor pattern, the first light-emitting pattern and the third semiconductor pattern on a reference plane at least partially overlap to form a first light-emitting portion; orthographic projections of the second semiconductor pattern, the second light-emitting pattern and the fourth semiconductor pattern on the reference plane at least partially overlap to form a second light-emitting portion; and the reference plane is parallel to a plane where the first semiconductor layer is located.

2 . A pixel circuit configured to drive the light-emitting device according to claim 1 , comprising:
a first control circuit coupled to a first scanning signal terminal, a first data signal terminal, a first voltage signal terminal and the first light-emitting portion of the light-emitting device, wherein the first control circuit is configured to, under control of a first scanning signal from the first scanning signal terminal and a first data signal from the first data signal terminal, control connection between the first voltage signal terminal and the first light-emitting portion, and control a luminance of the first light-emitting portion to be switched between a first gray scale and a second gray scale; and a second control circuit coupled to the first scanning signal terminal, the first voltage signal terminal and the second light-emitting portion of the light-emitting device, wherein the second control circuit is configured to, under control of the first scanning signal from the first scanning signal terminal, control connection between the first voltage signal terminal and the second light-emitting portion, and control a magnitude of a driving current flowing through the second light-emitting portion, wherein the second control circuit includes:
a second data writing sub-circuit, the second data writing sub-circuit being coupled to the first scanning signal terminal, a second data signal terminal and a second node, and being configured to transmit a second data signal from the second data signal terminal to the second node under the control of the first scanning signal from the first scanning signal terminal;
a second storage sub-circuit, the second storage sub-circuit being coupled to the second node and a third node, and being configured to store a voltage of the second node and adjust a voltage of the third node;
a first driving sub-circuit, the first driving sub-circuit being coupled to the third node, the first voltage signal terminal and a fourth node, and being configured to transmit a driving current to the fourth node under control of the voltage of the third node and a first voltage signal from the first voltage signal terminal;
a compensation sub-circuit, the compensation sub-circuit being coupled to the first scanning signal terminal, the fourth node and the third node, and being configured to compensate a threshold voltage of the first driving sub-circuit to the third node under the control of the first scanning signal from the first scanning signal terminal;
a voltage control sub-circuit, the voltage control sub-circuit being coupled to a second scanning signal terminal, a second voltage signal terminal and the second node, and being configured to transmit a second voltage signal from the second voltage signal terminal to the second node under control of a second scanning signal from the second scanning signal terminal;
a light-emitting control sub-circuit, the light-emitting control sub-circuit being coupled to an enable signal terminal, the fourth node and the second light-emitting portion, and being configured to transmit the driving current of the fourth node to the second light-emitting portion under control of an enable signal from the enable signal terminal; and
an initialization sub-circuit, the initialization sub-circuit being coupled to a reset signal terminal, the second voltage signal terminal and the second node, and being configured to transmit the second voltage signal from the second voltage signal terminal to the second node under control of a reset signal from the reset signal terminal.

3 . The pixel circuit according to claim 2 , wherein the first control circuit includes:
a first data writing sub-circuit, the first data writing sub-circuit being coupled to the first scanning signal terminal, the first data signal terminal and a first node, and being configured to transmit the first data signal from the first data signal terminal to the first node under the control of the first scanning signal from the first scanning signal terminal; a switch control sub-circuit, the switch control sub-circuit being coupled to the first node, the first voltage signal terminal and the first light-emitting portion, and being configured to control the connection between the first voltage signal terminal and the first light-emitting portion under control of a voltage of the first node; and a first storage sub-circuit, the first storage sub-circuit being coupled to the first voltage signal terminal and the first node, and being configured to store and maintain the voltage of the first node.

4 . The pixel circuit according to claim 3 , wherein
the first data writing sub-circuit includes:
a first transistor, a control electrode of the first transistor being coupled to the first scanning signal terminal, a first electrode of the first transistor being coupled to the first data signal terminal, and a second electrode of the first transistor being coupled to the first node;
the switch control sub-circuit includes:
a second transistor, a control electrode of the second transistor being coupled to the first node, a first electrode of the second transistor being coupled to the first voltage signal terminal, and a second electrode of the second transistor being coupled to the first light-emitting portion; and
the first storage sub-circuit includes:
a first storage capacitor, a first end of the first storage capacitor being coupled to the first node, and a second end of the first storage capacitor being coupled to the first voltage signal terminal.

5 . The pixel circuit according to claim 2 , wherein
the second data writing sub-circuit includes:
a third transistor, a control electrode of the third transistor being coupled to the first scanning signal terminal, a first electro

Assignees

• Boe Technology Group Co Ltd

Inventors

• Liu Weixing
• Peng Kuanjun
• Li Xiaolong
• Teng Wanpeng
• Qin Bin
• Chen Wanzhi
• Zhang Fangzhen
• Zhang Chunfang
• Xu Zhiqiang

Classifications

• H10W90/00

  Package configurations · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0626

  for control of overall brightness · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title