Metallization of solar cells

US12532569B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12532569-B2
Application numberUS-202418783283-A
CountryUS
Kind codeB2
Filing dateJul 24, 2024
Priority dateDec 20, 2013
Publication dateJan 20, 2026
Grant dateJan 20, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Approaches for the metallization of solar cells and the resulting solar cells are described. In an example, a method of fabricating a solar cell involves forming a barrier layer on a semiconductor region disposed in or above a substrate. The semiconductor region includes monocrystalline or polycrystalline silicon. The method also involves forming a conductive paste layer on the barrier layer. The method also involves forming a conductive layer from the conductive paste layer. The method also involves forming a contact structure for the semiconductor region of the solar cell, the contact structure including at least the conductive layer.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method of fabricating a solar cell, the method comprising: forming a first tunnel dielectric layer vertically over and directly on a silicon substrate; forming an emitter region vertically over and directly on the first tunnel dielectric layer; forming a second tunnel dielectric layer vertically over and directly on the emitter region; and forming a conductive contact vertically over and directly on the second tunnel dielectric layer, the conductive contact comprising a metal and silicon. 2 . The method of claim 1 , wherein forming the first tunnel dielectric layer comprises forming a first silicon oxide layer, and forming the second tunnel dielectric layer comprises forming a second silicon oxide layer. 3 . The method of claim 1 , wherein forming the second tunnel dielectric layer comprises forming a layer selected from the group consisting of a silicon oxide layer, a silicon oxynitride layer, and an aluminum oxide layer. 4 . The method of claim 1 , wherein forming the emitter region comprises forming a polycrystalline silicon layer. 5 . The method of claim 1 , wherein forming the conductive contact comprises forming a layer comprising aluminum. 6 . The method of claim 1 , wherein forming the emitter region comprises forming an n-type emitter region. 7 . The method of claim 1 , wherein forming the emitter region comprises forming a p-type emitter region. 8 . A method of fabricating a solar cell, the method comprising: forming a first tunnel dielectric layer on a silicon substrate; forming an emitter region on the first tunnel dielectric layer; forming a second tunnel dielectric layer on the emitter region; and forming a conductive contact on the second tunnel dielectric layer, the conductive contact comprising a metal and silicon, and the conductive contact having a lateral width the same as a lateral width of the second tunnel dielectric layer. 9 . The method of claim 8 , wherein the emitter region is vertically over the first tunnel dielectric layer, the second tunnel dielectric layer is vertically over the emitter region, and the conductive contact is vertically over the second tunnel dielectric layer. 10 . The method of claim 8 , wherein the first tunnel dielectric layer is a first silicon oxide layer, and the second tunnel dielectric layer is a second silicon oxide layer. 11 . The method of claim 8 , wherein the second tunnel dielectric layer is a layer selected from the group consisting of a silicon oxide layer, a silicon oxynitride layer, and an aluminum oxide layer. 12 . The method of claim 8 , wherein the emitter region comprises polycrystalline silicon. 13 . The method of claim 8 , wherein the conductive contact comprises aluminum. 14 . The method of claim 8 , wherein the emitter region is an n-type emitter region. 15 . The method of claim 8 , wherein the emitter region is a p-type emitter region. 16 . A method of fabricating a back contact solar cell, the method comprising: providing a monocrystalline silicon substrate having a back surface opposite a light-receiving surface; forming a first silicon oxide layer on the monocrystalline silicon substrate; forming a polycrystalline silicon layer on the first silicon oxide layer; forming a second silicon oxide layer on the polycrystalline silicon layer; and forming a conductive layer on the second silicon oxide layer, the conductive layer comprising a metal and silicon, and the conductive layer having a lateral width the same as a lateral width of the second silicon oxide layer. 17 . The method of claim 16 , wherein the polycrystalline silicon layer is vertically over the first silicon oxide layer, the second silicon oxide layer is vertically over the polycrystalline silicon layer, and the conductive layer is vertically over the second silicon oxide layer. 18 . The method of claim 16 , wherein the conductive layer comprises aluminum. 19 . The method of claim 16 , wherein the polycrystalline silicon layer is an n-type polycrystalline silicon layer. 20 . The method of claim 16 , wherein the polycrystalline silicon layer is a p-type polycrystalline silicon layer.

Assignees

Inventors

Classifications

  • for photovoltaic devices or modules · CPC title

  • the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells · CPC title

  • Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side · CPC title

  • Manufacturing or production processes characterised by the final manufactured product · CPC title

  • Monocrystalline silicon PV cells · CPC title

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What does patent US12532569B2 cover?
Approaches for the metallization of solar cells and the resulting solar cells are described. In an example, a method of fabricating a solar cell involves forming a barrier layer on a semiconductor region disposed in or above a substrate. The semiconductor region includes monocrystalline or polycrystalline silicon. The method also involves forming a conductive paste layer on the barrier layer. T…
Who is the assignee on this patent?
Maxeon Solar Pte Ltd
What technology area does this patent fall under?
Primary CPC classification H10F77/219. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 20 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).