Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12532452-B2
Application number	US-202318149188-A
Country	US
Kind code	B2
Filing date	Jan 3, 2023
Priority date	May 6, 2022
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes a substrate and a stacked structure located on the substrate; a doped region located between the stacked structure and the substrate, where on a section perpendicular to the substrate, the doped region includes a top doped region, a bottom doped region, and an intermediate doped region connecting the top doped region to the bottom doped region, in a direction parallel to the substrate, the top doped region has a first width, the bottom doped region has a second width, the intermediate doped region has a gradually changing third width, the first width is greater than the second width, and the third width decreases gradually along a direction away from the substrate.

First claim

The invention claimed is:

1 . A semiconductor structure, comprising:
a substrate and a stacked structure located on the substrate;
a doped region located between the stacked structure and the substrate, wherein on a section perpendicular to the substrate, the doped region comprises a top doped region, a bottom doped region, and an intermediate doped region connecting the top doped region to the bottom doped region, in a direction parallel to the substrate, the top doped region has a first width, the bottom doped region has a second width, the intermediate doped region has a gradually changing third width, the first width is greater than the second width, and the gradually changing third width decreases gradually along a direction away from the substrate;
wherein the stacked structure comprises a gate stack structure, the gate stack structure comprises a gate dielectric layer in contact with the doped region, and a first gate conductive layer and a second gate conductive layer on the gate dielectric layer, and on the section perpendicular to the substrate, the first gate conductive layer is thinner than the second gate conductive layer; and
the stacked structure further comprises a dielectric stack structure on the top doped region, the gate stack structure is located on the intermediate doped region and the bottom doped region, and a top surface of the dielectric stack structure is higher than a top surface of the gate stack structure.

2 . The semiconductor structure according to claim 1 , wherein on the section perpendicular to the substrate, the second gate conductive layer has a first thickness; and
in the direction parallel to the substrate, the first thickness increases gradually from the bottom doped region to the top doped region.

3 . The semiconductor structure according to claim 1 , further comprising a first dielectric layer, wherein the first dielectric layer is located between the stacked structure and the top doped region, the gate dielectric layer is connected to the first dielectric layer, the gate dielectric layer is in contact with the first gate conductive layer, and the first dielectric layer is in contact with the second gate conductive layer; and
on the section perpendicular to the substrate, thicknesses of the gate dielectric layer and the first dielectric layer are the same or different.

4 . The semiconductor structure according to claim 1 , wherein the dielectric stack structure comprises a second dielectric layer and a third dielectric layer, on the section perpendicular to the substrate, a top surface of the second dielectric layer is higher than a top surface of the first gate conductive layer, the top surface of the second dielectric layer is lower than a top surface of the second gate conductive layer, and a top surface of the third dielectric layer is higher than the top surface of the second gate conductive layer.

5 . The semiconductor structure according to claim 1 , further comprising a first plug, wherein the first plug penetrates through the dielectric stack structure, and is in contact with the top doped region.

6 . The semiconductor structure according to claim 1 , wherein the first gate conductive layer comprises a work function regulating material, and the second gate conductive layer comprises a metal conductive material.

7 . The semiconductor structure according to claim 1 , wherein doping types of the bottom doped region and the intermediate doped region are the same, and doping types of the top doped region and the intermediate doped region are the same or different.

8 . The semiconductor structure according to claim 1 , further comprising an isolation structure covering the stacked structure.

9 . The semiconductor structure according to claim 8 , further comprising a source region and a drain region that are disposed in the substrate, and are located at two sides of the stacked structure respectively.

10 . The semiconductor structure according to claim 9 , further comprising:
a second plug, wherein the second plug is disposed perpendicular to the substrate, and is in contact with the source region; and a third plug, wherein the third plug is disposed perpendicular to the substrate, and is in contact with the drain region.

Assignees

• Changxin Memory Tech Inc
• Changxin Jidian Beijing Memory Tech Co Ltd

Inventors

• Liu Xiang
• Yang Bin

Classifications

• H10D64/0133

  at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall · CPC title

• H10D64/021

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title