Power delivery control circuit

Patent metadata

Field	Value
Publication number	US-12531487-B2
Application number	US-202418771926-A
Country	US
Kind code	B2
Filing date	Jul 12, 2024
Priority date	Dec 13, 2018
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

A power circuit is disclosed. The power circuit includes an input node, a plurality of inductors each connected to an output node, a plurality of phases each configured to provide current to one of the inductors, and a control circuit configured to trigger the phases. The phases are configured to provide current to one of the inductors in response to being triggered by the control circuit, the control circuit is configured to determine a variable time difference between a first phase being triggered and a second phase being triggered, and the time difference is based at least in part on a voltage difference between an input voltage at the input node and an output voltage at the output node.

First claim

What is claimed is:

1 . A method of operating a circuit, the method comprising:
delivering, by a first power converter phase, a first predetermined quantity of charge to a power output terminal; delivering, by a second power converter phase, a second predetermined quantity of charge to the power output terminal; providing a first inductor coupled directly between the first power converter phase and the power output terminal; providing a second inductor coupled directly between the second power converter phase and the power output terminal; generating, by a control circuit, a plurality of trigger signals to repeatedly trigger the first and second power converter phases, wherein the control circuit is arranged to cause the trigger signals to have a variable frequency; controlling, by the control circuit, a time delay between the first power converter phase delivering the first predetermined quantity of charge and the second power converter phase delivering the second predetermined quantity of charge; wherein the time delay is based on is based on a difference between a voltage at the power output terminal and a reference voltage and on; and wherein the first predetermined quantity of charge and the second predetermined quantity of charge are substantially equal.

2 . The method of claim 1 , further comprising:
delivering, by a third power converter phase, a third predetermined quantity of charge to the power output terminal; and providing a third inductor coupled directly between the third power converter phase and the power output terminal.

3 . The method of claim 2 , wherein the time delay is a first time delay and wherein the method further comprises controlling, by the control circuit, a second time delay between the second power converter phase delivering the second predetermined quantity of charge and the third power converter phase delivering the third predetermined quantity of charge.

4 . The method of claim 3 , wherein the second time delay is based on the difference between a voltage at the power output terminal and the reference voltage and on the variable frequency.

5 . The method of claim 4 , wherein the first time delay is equal to the second time delay.

6 . The method of claim 5 , wherein the second predetermined quantity of charge and the third predetermined quantity of charge are substantially equal.

7 . The method of claim 1 , wherein the time delay is further based on the variable frequency.

8 . The method of claim 7 , further comprising reducing, by the control circuit, the time delay when the difference between the voltage at the power output terminal and the reference voltage is increased.

9 . The method of claim 7 , further comprising increasing, by the control circuit, the time delay when the difference between the voltage at the power output terminal and the reference voltage is reduced.

10 . The method of claim 7 , further comprising providing an error amplifier.

11 . The method of claim 10 , further comprising receiving, by the error amplifier, the voltage at the power output terminal and the reference voltage, and generating an error voltage based the difference between the voltage at the power output terminal and the reference voltage.

12 . The method of claim 11 , further comprising providing a voltage to time circuit coupled to the error amplifier.

13 . The method of claim 12 , further comprising receiving, by the voltage to time circuit, the error voltage and generating a clock having a period equal to the time delay.

14 . The method of claim 13 , further comprising providing a phaser circuit coupled to the voltage to time circuit.

15 . The method of claim 14 , further comprising receiving, by the phaser circuit, the clock and generating first and second phaser signals having start times spaced apart by the time delay.

16 . A circuit comprising:
a control circuit; a first power converter phase arranged to deliver a first predetermined quantity of charge to a power output terminal; a second power converter phase arranged to deliver a second predetermined quantity of charge to the power output terminal; a first inductor coupled directly between the first power converter phase and the power output terminal without having a current sensor connected between the first power converter phase and the power output terminal; a second inductor coupled directly between the second power converter phase and the power output terminal; wherein the control circuit is arranged to generate a plurality of trigger signals to repeatedly trigger the first and second power converter phases; and wherein the first predetermined quantity of charge and the second predetermined quantity of charge are substantially equal; wherein the first power converter phase comprises a comparator arranged to generate a signal that is indicative of a current in the first inductor; wherein the control circuit is arranged to cause the trigger signals to have a variable frequency; wherein the control circuit is arranged to control a time delay between the first power converter phase delivering the first predetermined quantity of charge and the second power converter phase delivering the second predetermined quantity of charge; and wherein the time delay is based on a difference between a voltage at the power output terminal and a reference voltage, and on the variable frequency.

17 . The circuit of claim 16 , wherein the control circuit is further arranged to reduce the time delay when the difference between the voltage at the power output terminal and the reference voltage is increased.

Assignees

• Empower Semiconductor Inc

Inventors

• Lidsky David
• Phillips Timothy Alan
• Oak Parag
• Jaganathan Shrinivasan

Classifications

• H02M3/155

  using semiconductor devices only · CPC title

• H02M1/0095

  Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/1586 Primary

  switched with a phase shift, i.e. interleaved · CPC title