Dataflow gaskets for handling data streams

Patent metadata

Field	Value
Publication number	US-12530308-B2
Application number	US-202418780879-A
Country	US
Kind code	B2
Filing date	Jul 23, 2024
Priority date	Jul 25, 2023
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

Apparatus and methods for facilitating data movement among circuit blocks are disclosed. In certain embodiments, an integrated circuit (IC) includes a network of dataflow gaskets including a first dataflow gasket coupled to a first circuit block and a second dataflow gasket coupled to a second circuit block. The first circuit block can write to the second circuit block by programming output stream registers of the first dataflow gasket for an outgoing write stream that includes a header identifying the second dataflow gasket. The header can be provided by the first dataflow gasket to the second dataflow gasket over the network, and in response to the header reaching the second dataflow gasket, the second dataflow gasket can program the input stream registers of the second dataflow gasket for an incoming read stream.

First claim

What is claimed is:

1 . An integrated circuit (IC) comprising:
a plurality of circuit blocks including a first circuit block and a second circuit block; and a plurality of dataflow gaskets electrically connected by a network of gasket interconnect, the plurality of dataflow gaskets comprising a first dataflow gasket comprising input stream registers, an input memory coupled to the first circuit block, output stream registers and an output memory coupled to the first circuit block, and a second dataflow gasket comprising output stream registers, an output memory coupled to the second circuit block, input stream registers and an input memory coupled to the second circuit block, wherein the first circuit block is configured to write data to the second circuit block by programming the output stream registers of the first dataflow gasket for an outgoing write stream that includes a header identifying the second dataflow gasket, and by the second dataflow gasket programming the input stream registers of the second dataflow gasket for an incoming read stream in response to the header reaching the second dataflow gasket over the network, wherein the first circuit block is configured to read from the second circuit block by programming the input stream registers of the first dataflow gasket for an incoming read stream, and by the second dataflow gasket programming the output stream registers of the second dataflow gasket for an outgoing write stream.

2 . The IC of claim 1 , wherein the data flows through the network from the output memory of the first dataflow gasket to the input memory of the second dataflow gasket.

3 . The IC of claim 2 , wherein the input memory of the second dataflow gasket is configured to activate an interrupt signal for the second circuit block in response to receiving the data.

4 . The IC of claim 2 , wherein the first circuit block writes the data to the output memory of the first dataflow gasket using a circular buffer of the first dataflow gasket.

5 . The IC of claim 1 , wherein an address space of the first circuit block is separate from an address space of the first dataflow gasket and an address space of the second dataflow gasket.

6 . The IC of claim 1 , wherein the first circuit block comprises a digital signal processor, a central processing unit, a neural processing unit, a reconfigurable compute unit, a digital-to-analog converter (DAC), or an analog-to-digital converter (ADC).

7 . The IC of claim 1 , wherein the plurality of dataflow gaskets further comprises a third dataflow gasket, wherein the data is configured to pass through the third dataflow gasket in route from the first dataflow gasket to the second dataflow gasket.

8 . The IC of claim 1 , wherein the first dataflow gasket comprises a first crossbar switch connected to the network, and the second dataflow gasket comprises a second crossbar switch connected to the network.

9 . The IC of claim 1 , wherein the input memory is readable by the second circuit block and the output memory is writable by the first circuit block.

10 . The IC of claim 1 , wherein the second dataflow gasket includes an input port connected to the network, and a crossbar switch configured to connect the input port to the input memory in response to the header reaching the second dataflow gasket.

11 . The IC of claim 10 , wherein the second dataflow gasket further includes an output port connected to the network, wherein the crossbar switch is further configured to connect the output memory to the output port to send the outgoing write stream, and to connect the input port to the output port for a data stream that does not identify the second dataflow gasket.

12 . The IC of claim 1 , wherein the second dataflow gasket is further configured to fork a received data stream into a first data stream for a first destination and a second data stream for a second destination.

13 . The IC of claim 1 , wherein the second dataflow gasket is further configured to merge a first data stream from a first source and a second data stream from a second source.

14 . An integrated circuit (IC) comprising: The IC of claim 1 ,
a plurality of circuit blocks including a first circuit block and a second circuit block; and a plurality of dataflow gaskets electrically connected by a network of gasket interconnect, the plurality of dataflow gaskets comprising a first dataflow gasket comprising output stream registers and an output memory coupled to the first circuit block, and a second dataflow gasket comprising input stream registers and an input memory coupled to the second circuit block, wherein the first circuit block is configured to write data to the second circuit block by programming the output stream registers of the first dataflow gasket for an outgoing write stream that includes a header identifying the second dataflow gasket, and by the second dataflow gasket programming the input stream registers of the second dataflow gasket for an incoming read stream in response to the header reaching the second dataflow gasket over the network wherein the second dataflow gasket further comprises a register file storing a gasket identifier, and a packet handling circuit configured to compare the header to the gasket identifier.

15 . A method of dataflow in an integrated circuit (IC), the method comprising:
initiating a write from a first circuit block of the IC to a second circuit block of the IC using the first circuit block; programming output stream registers of a first dataflow gasket of the IC for an outgoing write stream using the first circuit block, the first dataflow gasket including an output memory coupled to the first circuit block, and the outgoing write stream including a header identifying a second dataflow gasket of the IC that is electrically connected to the first dataflow gasket by a network of gasket interconnect; programming input stream registers of the second dataflow gasket for an incoming read stream in response to the header reaching the second dataflow gasket over the network, the second dataflow gasket further comprising an input memory coupled to the second circuit block; and initiating a read of the second circuit block from the first circuit block by programming input stream registers of the first dataflow gasket for an incoming read stream, and by programming output stream registers of the second dataflow gasket for an outgoing write stream.

16 . The method of claim 15 , further comprising providing the data through the network from the output memory of the first dataflow gasket to the input memory of the second dataflow gasket.

17 . The method of claim 16 , further comprising writing the data from the first circuit block to the output memory of the first dataflow gasket using a circular buffer of the first dataflow gasket.

18 . The method of claim 15 , wherein the second dataflow gasket further comprises a register file storing a gasket identifier, the method further comprising comparing the header to the gasket identifier using a packet handling circuit of the second dataflow gasket.

19 . The method of claim 15 , further comprising feeding the data through a third dataflow gasket in route from the first dataflow gasket to the second dataflow gasket over the network.

20 . The method of claim 15 , further comprising reading the input memory using the second circuit block and writing the output memory using the first circuit block.

Assignees

• Analog Devices Inc

Inventors

• Mayer Christopher
• Desai Sudhir
• Azizimazreah Arash

Classifications

• G06F2213/40

  Bus coupling · CPC title

• G06N3/063

  using electronic means · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06F15/173

  using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake · CPC title

• G06F13/36 Primary

  for access to common bus or bus system · CPC title