Cryptographic block locking in a non-volatile memory device

Patent metadata

Field	Value
Publication number	US-12530135-B2
Application number	US-202217804153-A
Country	US
Kind code	B2
Filing date	May 26, 2022
Priority date	May 26, 2022
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

A memory device may be configured to receive a command to access a block of memory that is one of multiple blocks of memory included in the memory device. The memory device may be configured to receive a cryptographic signature associated with the command. The memory device may be configured to enable or disable access to the block of memory based on the command and based on the cryptographic signature. The memory device may be capable of separately restricting access to each individual block of the multiple blocks.

First claim

What is claimed is:

1 . A memory device, comprising:
one or more components configured to:
receive a command to access a block of memory that is one of multiple blocks of memory included in the memory device;
identify whether read access, write access, or erase access to the block of memory is restricted; and
receive a cryptographic signature associated with the command; and
latch circuitry configured to enable or disable access to the block of memory, wherein the latch circuitry comprises:
a lock circuit that stores information indicating whether the block of memory is locked for one or more functions;
a NOR gate, configured to receive an input of a verification signal and an input based on the lock circuit; and
a multiplexer configured to receive an input from an output of the NOR gate, wherein access to the block of memory is enabled or disabled based on an output of the multiplexer.

2 . The memory device of claim 1 , wherein the one or more components are further configured to:
receive an indication of a block address that identifies the block; and determine, based on the block address, whether access to the block is restricted; and wherein the one or more components, to enable or disable access to the block, are configured to enable or disable access to the block of memory further based on determining whether access to the block is restricted.

3 . The memory device of claim 1 ,
wherein the one or more components are further configured to output the verification signal that indicates whether the cryptographic signature is verified.

4 . The memory device of claim 1 , wherein the one or more components are further configured to enable or disable access to the block of memory, for each command to access the block of memory, based on a corresponding cryptographic signature received in connection with that command.

5 . The memory device of claim 1 , wherein the one or more components are further configured to enable or disable access to the block of memory, for each command to access the block of memory, based on a corresponding cryptographic signature received in connection with that command unless access to the block has been enabled for multiple commands.

6 . The memory device of claim 1 , wherein the one or more components are further configured to:
receive an instruction to enable access to the block of memory for multiple commands; store an indication that access to the block of memory is enabled based on verifying the cryptographic signature for the command; receive another command to access the block of memory; and enable access to the block of memory for the other command based on the stored indication that access to the block of memory is enabled.

7 . The memory device of claim 6 , wherein the one or more components are further configured to store an indication that access to the block of memory for multiple commands is disabled based on at least one of:
reception of an instruction to disable access to the block of memory for multiple commands; reception of a command that identifies another block of memory that is different from the block of memory; or powering up or powering down of the memory device.

8 . A device, comprising:
a controller configured to:
receive a command to access a block of non-volatile memory;
receive a cryptographic signature associated with the command; and
determine whether the block is associated with an access restriction related to the command; and
latch circuitry, separate from the block, configured to enable or disable access to the block based on whether the block is associated with the access restriction or based on the cryptographic signature, wherein the latch circuitry comprises:
one or more lock circuits that store information indicating whether the block is locked for one or more functions;
one or more NOR gates, each configured to receive an input of a verification signal and an input based on the one or more lock circuits; and
a multiplexer configured to receive an input from an output of the one or more NOR gates, wherein access to the block is enabled or disabled based on an output of the multiplexer.

9 . The device of claim 8 , wherein the controller, to determine whether the block is associated with the access restriction, is configured to:
receive an indication of a block address that identifies the block; and identify one or more block attributes that are associated with the block in a record, wherein the one or more block attributes indicate whether the block is associated with a read access restriction, a write access restriction, or an erase access restriction.

10 . The device of claim 8 , wherein the controller, to enable or disable access to the block, is configured to:
determine, based on a block address of the block, that the block is not associated with the access restriction; and enabling access to the block based on determining that the block is not associated with the access restriction.

11 . The device of claim 10 , wherein the controller, to determine that the block is not associated with the access restriction, is configured to:
identify a command type associated with the command, wherein the command type is one of a read command type, a write command type, or an erase command type; and determine that the block is not associated with the access restriction for the command type.

12 . The device of claim 8 , wherein the controller, to enable or disable access to the block, is configured to:
determine, based on a block address of the block, that the block is associated with the access restriction; determine that the cryptographic signature is verified; and enable access to the block based on determining that the block is associated with the access restriction and that the cryptographic signature is verified.

13 . The device of claim 12 , wherein the controller, to determine that the block is associated with the access restriction, is configured to:
identify a command type associated with the command, wherein the command type is one of a read command type, a write command type, or an erase command type; and determine that the block is associated with the access restriction for the command type.

14 . The device of claim 8 , wherein the controller, to enable or disable access to the block, is configured to:
determine, based on a block address of the block, that the block is associated with the access restriction; determine that the received cryptographic signature is not verified; and disable access to the block based on determining that the block is associated with the access restriction and that the cryptographic signature is not verified.

15 . A device, comprising:
a controller configured to:
receive a command to access a block of non-volatile memory, wherein the device stores:
a first indication indicating whether a first type of access to the block of non-volatile memory is restricted,
a second indication indicating whether a second type of access to the block of non-volatile memory is restricted, and
a third indication indicating whether a third type of access to the block of non-volatile memory is restricted;

receive a cryptographic signature associated with the command; and
output a verification signal based on the cryptographic signature; and
latch circuitry, separate from the block of non-volatile memory, configured to:
receive the verification signal; and
enable or disable access to the block of non-volatile memory, associated with the latch circuitry, based on the verification signal,
wherein the latch circuitry comprises:
o

Assignees

• Micron Technology Inc

Inventors

• Binfet Jeremy
• Dover Lance Walker
• Strong Robert William
• Di Francesco Walter
• Vali Tommaso
• Mcneil Jr Jeffrey Scott

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F21/44

  Program or device authentication · CPC title

• G06F3/0622 Primary

  in relation to access · CPC title

• G06F21/79 Primary

  in semiconductor storage media, e.g. directly-addressable memories · CPC title