Power aware thermal mitigation framework

Patent metadata

Field	Value
Publication number	US-12530064-B2
Application number	US-202418428959-A
Country	US
Kind code	B2
Filing date	Jan 31, 2024
Priority date	Jan 31, 2024
Publication date	Jan 20, 2026
Grant date	Jan 20, 2026

Abstract

Aspects relate to mechanisms for providing a power aware thermal mitigation framework for a system-on-chip (SoC) of a device (e.g., a mobile device). A thermal controller of the SoC is configured to calculate a respective power of each of a plurality of electronic control units (ECUs) on the SoC at run time. The ECUs may include, for example, central processing units (CPUs), graphic processing units (GPUs), neural signal processors (NSPs), etc. In response to a skin temperature of the device exceeding a threshold (e.g., a thermal limit of the device), the thermal controller may then be configured to apply at least one thermal mitigation action to at least one ECU of the plurality of ECUs based on the respective power of each of the ECUs.

First claim

What is claimed is:

1 . An apparatus, comprising:
a plurality of electronic control units (ECUs) on a system-on-chip (SoC); and a thermal controller configured to calculate a respective power of each of a plurality of electronic control units (ECUs) on the SoC at run time and to apply at least one thermal mitigation action to at least one ECU of the plurality of ECUs based on the respective power of each of the plurality of ECUs in response to a skin temperature of the apparatus exceeding a threshold, wherein the thermal controller is further configured to:
calculate a respective dynamic power of each of the plurality of ECUs,
calculate a respective leakage power of each of the plurality of ECUs, and
add the respective dynamic power to the respective leakage power to produce the respective power of each of the plurality of ECUs.

2 . The apparatus of claim 1 , wherein the thermal controller is further configured to:
apply a first thermal mitigation action to a first ECU of the plurality of ECUs, a first power of the first ECU being higher than the respective power of other ECUs of the plurality of ECUs.

3 . The apparatus of claim 2 , wherein the thermal controller is further configured to:
update the respective power of each of the plurality of ECUs on the SoC based on the first thermal mitigation action to produce a respective updated power of each of the plurality of ECUs; and apply a second thermal mitigation action to a second ECU of the plurality of ECUs based on the respective updated power of each of the plurality of ECUs and in response to the skin temperature of the apparatus continuing to exceed the threshold, a second power of the second ECU being higher than the respective power of remaining ECUs of the plurality of ECUs.

4 . The apparatus of claim 1 , wherein the thermal controller is further configured to:
calculate the respective dynamic power of each of the plurality of ECUs based on a respective reference dynamic power for each of the plurality of ECUs and a respective dynamic scaling factor for each of the plurality of ECUs, wherein the respective reference dynamic power for each of the plurality of ECUs is associated with a respective reference ECU for each of the plurality of ECUs, the respective reference dynamic power being stored on the respective ECU.

5 . The apparatus of claim 4 , wherein the thermal controller is further configured to:
identify a respective reference settling voltage and a respective device settling voltage for each of the plurality of ECUs based on a respective operating frequency of each of the plurality of ECUs, the respective reference settling voltage being associated with the respective reference ECU and stored on the respective ECU, the respective device settling voltage being associated with the respective ECU and stored on the respective ECU; and calculate the respective dynamic scaling factor of each of the plurality of ECUs based on the respective reference settling voltage and the respective device settling voltage.

6 . The apparatus of claim 1 , wherein the thermal controller is further configured to:
calculate the respective leakage power of each of the plurality of ECUs based on a respective reference leakage power for each of the plurality of ECUs and a respective leakage scaling factor for each of the plurality of ECUs, wherein the respective reference leakage power for each of the plurality of ECUs is associated with a respective reference ECU for each of the plurality of ECUs, the respective reference leakage power being stored on the respective ECU.

7 . The apparatus of claim 6 , wherein the thermal controller is further configured to:
identify a respective reference settling voltage and a respective device settling voltage for each of the plurality of ECUs based on a respective operating frequency of each of the plurality of ECUs, the respective reference settling voltage being associated with the respective reference ECU and stored on the respective ECU of the plurality of ECUs, the respective device settling voltage being associated with the respective ECU and stored on the respective ECU; identify a respective reference leakage current associated with the respective reference ECU and a respective device leakage current associated with the respective ECU for each of the plurality of ECUs based on a respective junction temperature of each of the plurality of ECUs; and calculate the respective leakage scaling factor of each of the plurality of ECUs based on the respective reference settling voltage, the respective device settling voltage, the respective reference leakage current, and the respective device leakage current.

8 . The apparatus of claim 7 , wherein the thermal controller is further configured to:
calculate a respective fraction of the respective device leakage current to the respective reference leakage current for each of the plurality of ECUs; and multiply a respective junction temperature scaling factor to the respective fraction.

9 . The apparatus of claim 1 , wherein the at least one thermal mitigation action comprises at least one of throttling an operating frequency or throttling a clock of the at least one ECU.

10 . A method of thermal mitigation on a system-on-chip (SoC) of a device, the method comprising:
calculating a respective power of each of a plurality of electronic control units (ECUs) on the SoC at run time, wherein the calculating the respective power of each of the plurality of ECUs comprises:
calculating a respective dynamic power of each of the plurality of ECUs,
calculating a respective leakage power of each of the plurality of ECUs, and
adding the respective dynamic power to the respective leakage power to produce the respective power of each of the plurality of ECUs; and
applying at least one thermal mitigation action to at least one ECU of the plurality of ECUs based on the respective power of each of the plurality of ECUs in response to a skin temperature of the device exceeding a threshold.

11 . The method of claim 10 , wherein the applying the at least one thermal mitigation action further comprises:
applying a first thermal mitigation action to a first ECU of the plurality of ECUs, a first power of the first ECU being higher than the respective power of other ECUs of the plurality of ECUs.

12 . The method of claim 11 , further comprising:
updating the respective power of each of the plurality of ECUs on the SoC based on the first thermal mitigation action to produce a respective updated power of each of the plurality of ECUs; and applying a second thermal mitigation action to a second ECU of the plurality of ECUs based on the respective updated power of each of the plurality of ECUs and in response to the skin temperature of the device continuing to exceed the threshold, a second power of the second ECU being higher than the respective power of remaining ECUs of the plurality of ECUs.

13 . The method of claim 10 , wherein the calculating the respective dynamic power of each of the plurality of ECUs further comprises:
calculating the respective dynamic power of each of the plurality of ECUs based on a respective reference dynamic power for each of the plurality of ECUs and a respective dynamic scaling factor for each of the plurality of ECUs, wherein the respective reference dynamic power for each of the plurality of ECUs is associated with a respective reference ECU for each of the plurality of ECUs, the respective reference dynamic power being stored on the respective ECU.

14 . The method of claim 13 , further comprising:
identifying a respective reference settling

Assignees

• Qualcomm Inc

Inventors

• Boddu Lakshmi Kanth
• Singh Rohit
• Karnam Venkat Naga Srikar

Classifications

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/206 Primary

  comprising thermal management · CPC title