Nitride-based semiconductor circuit and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12527063-B2
Application number	US-202217637461-A
Country	US
Kind code	B2
Filing date	Jan 7, 2022
Priority date	Jan 7, 2022
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

A nitride-based semiconductor circuit including a substrate structure, a nitride-based heterostructure, connectors, and connecting vias is provided. The substrate structure includes a first type semiconductor substrate, and a second type semiconductor substrate. The second type semiconductor substrate is embedded in a region of the first type semiconductor substrate. The first type semiconductor substrate has first dopants, and the second type semiconductor substrate has second dopants to form a pn junction between the first type semiconductor substrate and the second type semiconductor substrate. The nitride-based heterostructure is disposed on the substrate structure. The connectors are disposed on the nitride-based heterostructure. The connecting vias include a first interconnection and a second interconnection. The first interconnection electrically connects the first region of the first type semiconductor substrate to one of the connectors. The second interconnection electrically connects the second type semiconductor substrate to another one of the connectors.

First claim

The invention claimed is:

1 . A nitride-based semiconductor circuit comprising:
a substrate structure comprising:
a first type semiconductor substrate having a first region and a second region adjacent to the first region; and
a second type semiconductor substrate embedded in the second region of the first type semiconductor substrate, wherein a top surface of the first type semiconductor substrate and a top surface of the second type semiconductor substrate are substantially coplanar, and the first type semiconductor substrate has first dopants, and the second type semiconductor substrate has second dopants to form a pn junction between the first type semiconductor substrate and the second type semiconductor substrate;
a nitride-based heterostructure disposed on the substrate structure, a plurality of connectors disposed on the nitride-based heterostructure; and a plurality of connecting vias going through the nitride-based heterostructure, wherein the connecting vias comprise: a first interconnection electrically connecting the first region of the first type semiconductor substrate to one of the connectors; and a second interconnection electrically connecting the second type semiconductor substrate to another one of the connectors; wherein the connectors comprise a first and second source connectors, a first and second drain connectors, and a first and second gate connectors, wherein the first gate connector is located between the first source connector and the first drain connector, and the second gate connector is located between the second source connector and the second drain connector; wherein the nitride-based semiconductor circuit further comprising a second patterned conductive layer disposed on the connectors, wherein the second patterned conductive layer electrically connects to the connectors, and the second patterned conductive layer has a plurality of pads, and one of the pads electrically connects to the first source connector and the second drain connector.

2 . The nitride-based semiconductor circuit of claim 1 , wherein an interface between the first type semiconductor substrate and the second type semiconductor substrate is concave or concave-like from a cross-sectional perspective.

3 . The nitride-based semiconductor circuit of claim 1 , further comprising a first patterned conductive layer disposed between the connectors and the second patterned conductive layer, wherein the first patterned conductive layer electrically connects the connectors to the second patterned conductive layer.

4 . The nitride-based semiconductor circuit of claim 1 , wherein the pad electrically connected to the first source connector and the second drain connector overlays part of the pn junction and electrically connects to the second type semiconductor substrate.

5 . The nitride-based semiconductor circuit of claim 1 , wherein the pad electrically connected to the first source connector and the second drain connector overlays both the first region and the second region.

6 . The nitride-based semiconductor circuit of claim 1 , wherein the first interconnection electrically connects the first type semiconductor substrate to the second source connector, and the second interconnection electrically connects the second type semiconductor substrate to the first source connector.

7 . The nitride-based semiconductor circuit of claim 1 , wherein the first source connector, the first drain connector, and the first gate connector are disposed on the second type semiconductor substrate, and the second source connector, the second drain connector, and the second gate connector are disposed on the first type semiconductor substrate.

8 . The nitride-based semiconductor circuit of claim 1 , further comprising:
an oxide layer in contact with the second gate connector and isolated from the first gate connector; and a nitride layer in contact with the first gate connector.

9 . The nitride-based semiconductor circuit of claim 8 , wherein the second gate connector comprises:
a doped nitride-based semiconductor layer disposed on the nitride-based heterostructure and in direct contact with the oxide layer; and an electrode disposed on the doped nitride-based semiconductor layer.

10 . The nitride-based semiconductor circuit of claim 9 , wherein the electrode is isolated from the oxide layer.

11 . The nitride-based semiconductor circuit of claim 1 , wherein a projection of the second type semiconductor substrate on a top surface of the substrate structure is rectangle in shape.

12 . The nitride-based semiconductor circuit of claim 1 , wherein a projection of the second type semiconductor substrate on a top surface of the substrate structure is round in shape.

13 . The nitride-based semiconductor circuit of claim 1 , wherein the second interconnection passes through an interface formed between the nitride-based heterostructure and the second type semiconductor substrate to have an end portion embedded in the second type semiconductor substrate.

14 . A manufacturing method of a nitride-based semiconductor circuit comprising:
providing a substrate structure, wherein the substrate structure comprises a first type semiconductor substrate having first dopants, and the first type semiconductor substrate has a first region and a second region adjacent to the first region; and a second type semiconductor substrate embedded in the second region of the first type semiconductor substrate, wherein a top surface of the first type semiconductor substrate and a top surface of the second type semiconductor substrate are coplanar, and the second type semiconductor substrate has second dopants to form a pn junction between the first type semiconductor substrate and the second type semiconductor substrate; forming a nitride-based heterostructure on the substrate structure; forming a plurality of connectors on the nitride-based heterostructure; etching through the nitride-based heterostructure; and forming a plurality of connecting vias; wherein the connecting vias comprises: a first interconnection electrically connecting the first region of the first type semiconductor substrate to one of the connectors; and a second interconnection electrically connecting the second type semiconductor substrate to another one of the connectors; wherein the connectors comprise a first and second source connectors, a first and second drain connectors, and a first and second gate connectors, wherein the first gate connector is located between the first source connector and the first drain connector, and the second gate connector is located between the second source connector and the second drain connector; wherein the manufacturing method further comprising forming a second patterned conductive layer disposed on the connectors, wherein the second patterned conductive layer electrically connects to the connectors, and the second patterned conductive layer has a plurality of pads, and one of the pads electrically connects to the first source connector and the second drain connector.

15 . The manufacturing method of claim 14 , the step of providing the substrate structure includes:
providing a semiconductor substrate having the first dopants; and doping the second dopants to form the second type semiconductor substrate, wherein the rest of the semiconductor substrate form the first type semiconductor substrate.

16 . The manufacturing method of claim 14 , before the step of forming the second patterned conductive layer, further comprising forming a first patterned conductive layer on the connectors,

Assignees

• Innoscience Suzhou Technology Holding Co Ltd

Inventors

• Gao Wuhao
• Zhao Qiyue

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title