Method for saving ciphertext and apparatus

Patent metadata

Field	Value
Publication number	US-12526137-B2
Application number	US-202218003265-A
Country	US
Kind code	B2
Filing date	May 11, 2022
Priority date	May 24, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

This application provides a method for saving a ciphertext and an apparatus. The method includes: obtaining an encryption instruction, where the encryption instruction instructs to encrypt a file in an external memory; obtaining an eigenvalue of a first account identifier based on the encryption instruction; encrypting a first key by using the eigenvalue of the first account identifier to generate a first ciphertext, where the first key is used to encrypt a second key, and the second key is used to encrypt a first file in the external memory; encrypting the eigenvalue of the first account identifier to generate a second ciphertext; and storing the first ciphertext and the second ciphertext in a non-erasable partition.

First claim

What is claimed is:

1 . A chip, comprising:
at least one processor; and at least one non-transitory storage medium coupled to the at least one processor, the at least one non-transitory storage medium storing instructions that, when executed by the at least one processor, cause the chip to perform the following:
displaying an encryption setting interface of an external memory;
receiving a first operation that is performed by a user on the encryption setting interface;
encrypting a file in the external memory in response to the first operation;
receiving a second operation of the user;
displaying a factory reset setting interface in response to the second operation;
receiving a third operation that is performed by the user on the factory reset setting interface;
performing a factory reset in response to the third operation;
displaying an account verification interface;
receiving verification information that is input by the user on the account verification interface; and
when the verification information is verified, and when an operation in which the user accesses the file in the external memory is received, decrypting the file that is encrypted in the external memory;
wherein receiving the first operation that is performed by the user on the encryption setting interface comprises:
obtaining an encryption instruction, wherein the encryption instruction instructs to encrypt the file in the external memory; and
wherein the instructions, when executed by the at least one processor, cause the chip to further perform:
obtaining an eigenvalue of a first account identifier based on the encryption instruction;
encrypting a first key by using the eigenvalue of the first account identifier to generate a first ciphertext, wherein the first key is used to encrypt a second key, and the second key is used to encrypt the file in the external memory;
encrypting the eigenvalue of the first account identifier to generate a second ciphertext; and
storing the first ciphertext and the second ciphertext in a non-erasable partition.

2 . The chip according to claim 1 , wherein when the at least one processor executes the instructions, the chip is caused to further perform the following steps:
receiving a fourth operation that is performed by the user on the encryption setting interface; encrypting the file in the external memory in response to the fourth operation; receiving a fifth operation of the user; displaying a user reset setting interface in response to the fifth operation; receiving a sixth operation that is performed by the user on the user reset setting interface; performing a user reset in response to the sixth operation; displaying a lock screen password verification interface; receiving a lock screen password that is input by the user on the lock screen password verification interface; and when the lock screen password is verified, and when an operation in which the user accesses the file in the external memory is received, decrypting the file that is encrypted in the external memory.

3 . The chip according to claim 1 wherein when the at least one processor executes the instructions, the chip is caused to further perform the following steps:
obtaining indication information for switching an account;
verifying the first account identifier based on the indication information;
obtaining an eigenvalue of a second account identifier after the first account identifier is verified; and
updating the first ciphertext and the second ciphertext based on the eigenvalue of the second account identifier.

4 . The chip according to claim 1 wherein before the decrypting the encrypted file in the external memory, when the at least one processor executes the instructions, the chip is caused to further perform the following steps:
verifying the first account identifier based on the verification information after the factory reset is completed; and
when the first account identifier is verified successfully, decrypting the first ciphertext and the second ciphertext to generate the first key.

5 . The chip according to claim 4 , wherein the verifying the first account identifier based on the verification information comprises:
verifying the first account identifier based on the verification information, when a factory reset protection (FRP) state has been triggered.

6 . The chip according to claim 4 , wherein when the at least one processor executes the instructions, the chip is caused to further perform the following steps:
encrypting the first key by using an empty auth to generate a third ciphertext; encrypting the empty auth to generate a fourth ciphertext; and storing the third ciphertext and the fourth ciphertext in the non-erasable partition.

7 . The chip according to claim 6 , wherein when the at least one processor executes the instructions, the chip is caused to further perform the following steps:
copying the third ciphertext and the fourth ciphertext from the non-erasable partition to an erasable partition; generating the first key based on the third ciphertext and the fourth ciphertext in the erasable partition; and decrypting, based on the first key, the first file that is encrypted in the external memory.

8 . The chip according to claim 1 wherein the performing a factory reset in response to the third operation comprises:
obtaining a factory reset instruction that is triggered by the third operation on the factory reset setting interface; and
formatting data in the erasable partition based on the factory reset instruction.

9 . The chip according to claim 1 wherein the encrypting a first key by using the eigenvalue of the first account identifier comprises:
invoking a key management module to encrypt the first key by using the eigenvalue of the first account identifier; and
wherein the encrypting the eigenvalue of the first account identifier comprises:
invoking the key management module to encrypt the eigenvalue of the first account identifier.

10 . The chip according to claim 1 wherein the storing the first ciphertext and the second ciphertext in a non-erasable partition comprises:
invoking a trusted execution environment application programming interface to store the first ciphertext and the second ciphertext in the non-erasable partition.

11 . The chip according to claim 1 wherein the first key is further used to encrypt a third key, and the third key is used to encrypt a second file that is encrypted in the external memory.

12 . The chip according to claim 1 wherein when the at least one processor executes the instructions, the chip is caused to further perform the following steps:
obtaining an eigenvalue of a lock screen password based on the encryption instruction;
encrypting the first key by using the eigenvalue of the lock screen password to generate a fifth ciphertext;
encrypting the eigenvalue of the lock screen password to generate a sixth ciphertext; and
storing the fifth ciphertext and the sixth ciphertext in the erasable partition;
wherein the encrypting the first key by using the eigenvalue of the lock screen password comprises:
invoking a key management module to encrypt the first key by using the eigenvalue of the lock screen password; and

wherein the encrypting the eigenvalue of the lock screen password comprises:
invoking the key management module to encrypt the eigenvalue of the lock screen password.

13 . The chip according to claim 12 , wherein when the at least one processor executes the instructions, the chip is caused to further perform the following steps:
obtaining a user reset instruction that is triggered by a setting int

Assignees

• Honor Device Co Ltd

Inventors

• Yu Hongjian
• Li Shuang
• Wang Fei

Classifications

• G06F21/79 Primary

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F21/6209

  to a single file or object, e.g. in a secure envelope, encrypted and accessed using a key, or with access control rules appended to the object itself · CPC title

• G06F21/602

  Providing cryptographic facilities or services · CPC title

• H04L9/14 Primary

  using a plurality of keys or algorithms · CPC title

• G06F21/78 Primary

  to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title