Communication method and communication device

Patent metadata

Field	Value
Publication number	US-12526071-B2
Application number	US-202418413573-A
Country	US
Kind code	B2
Filing date	Jan 16, 2024
Priority date	May 22, 2014
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

A communication method includes executing a cyclic block permutation for a codeword generated based on a quasi-cyclic parity-check code including a repeat-accumulate quasi-cyclic low-density parity-check code, where the cyclic block permutation is permutation of cyclic blocks within the codeword, and mapping each bit of the codeword for which the cyclic block permutation is executed to any one of constellation point of a non-uniform constellation.

First claim

What is claimed is:

1 . A transmission method performed by a transmitter, the transmission method comprising:
generating, by a coding circuit of the transmitter, a codeword according to quasi-cyclic low-density parity-check coding such that the codeword consists of N cyclic blocks, the N cyclic blocks each consist of Q bits, each of N and Q is a positive integer, and a code rate of the codeword is 7/15; reordering, by an interleaving circuit of the transmitter, the N cyclic blocks; mapping, by a mapping circuit of the transmitter, bits in the codeword onto constellation points of a non-uniform 4096 QAM scheme to generate mapped bits after the N cyclic blocks are reordered; and generating, by a signaling circuit of the transmitter, a transmission signal by performing orthogonal frequency-division multiplexing (OFDM) modulation on the mapped bits, wherein the N cyclic blocks are reordered according to Table 1 which is associated with the code rate, and in the Table 1, the j-th block of Group-wise Interleaver Output indicates the index of the cyclic block after the N cyclic blocks are reordered, and the π(j)-th block of Group-wise Interleaver Input indicates the index of the cyclic block before the N cyclic blocks are reordered

TABLE 1

j−th
π (j)−th

block of
block of

Group−wise
Group−wise

Interleaver
Interleaver

output
input

0
59

1
122

2
161

3
93

4
37

5
112

6
111

7
62

8
42

9
102

10
119

11
72

12
60

13
144

14
34

15
120

16
46

17
31

18
129

19
172

20
149

21
94

22
65

23
9

24
0

25
76

26
13

27
61

28
3

29
70

30
40

31
78

32
127

33
35

34
145

35
28

36
48

37
162

38
92

39
73

40
6

41
134

42
66

43
160

44
133

45
101

46
4

47
5

48
87

49
106

50
79

51
104

52
168

53
163

54
170

55
57

56
83

57
44

58
54

59
110

60
30

61
50

62
82

63
10

64
148

65
98

66
41

67

Assignees

• Panasonic Holdings Corp

Inventors

• Klenner Peter
• Herrmann Frank
• Kimura Tomohiro

Classifications

• H04L27/3405

  Modifications of the signal space to increase the efficiency of transmission, e.g. reduction of the bit error rate, bandwidth, or average power · CPC title

• H04L1/0071

  Use of interleaving (interleaving per se H03M13/27) · CPC title

• H04L1/0058

  Block-coded modulation · CPC title

• H03M13/2778

  Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices · CPC title

• H03M13/255

  with Low Density Parity Check [LDPC] codes · CPC title