Interleaved sampling circuit

Patent metadata

Field	Value
Publication number	US-12525972-B2
Application number	US-202418409209-A
Country	US
Kind code	B2
Filing date	Jan 10, 2024
Priority date	Jan 10, 2024
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

Certain aspects of the present disclosure are directed towards an interleaved sampling circuit. The interleaved sampling circuit generally includes: a clock generator having an input coupled to a main clock node and having a plurality of non-overlapping clock output nodes; and a plurality of sampling circuits, each of the plurality of sampling circuits having a first clock input coupled to a respective one of the non-overlapping clock output nodes and a second clock input coupled to the main clock node.

First claim

The invention claimed is:

1 . An interleaved sampling circuit, comprising:
a clock generator having an input coupled to a main clock node and having a plurality of non-overlapping clock output nodes; and a plurality of sampling circuits, each of the plurality of sampling circuits having a first clock input coupled to a respective one of the non-overlapping clock output nodes and a second clock input coupled to the main clock node, wherein each of the plurality of sampling circuits comprises:
a first transistor having a gate coupled to the main clock node and a drain coupled to an output clock node; and
a sampling switch having a control input coupled to the output clock node.

2 . The interleaved sampling circuit of claim 1 , wherein each of the plurality of sampling circuits is coupled to an input voltage node and further comprises:
a capacitive element coupled to the sampling switch; and a quantizer coupled to the capacitive element, the sampling switch being coupled between the input voltage node and the quantizer.

3 . The interleaved sampling circuit of claim 1 , wherein each of the plurality of sampling circuits further comprises a second transistor having a gate configured to receive a signal complementary to a respective one of non-overlapping clock signals at the respective one of the non-overlapping clock output nodes and a drain coupled to the output clock node.

4 . The interleaved sampling circuit of claim 1 , wherein each of the plurality of sampling circuits further comprises:
a second transistor having a gate configured to receive a signal complementary to a respective one of non-overlapping clock signals at the respective one of the non-overlapping clock output nodes; and a third transistor having a gate configured to receive a signal complementary to a main clock signal at the main clock node, the second transistor and the third transistor being coupled in series between a voltage rail and the output clock node.

5 . The interleaved sampling circuit of claim 1 , wherein each of the plurality of sampling circuits further comprises:
a second transistor coupled between the output clock node and a boosted voltage node; and a third transistor coupled between a gate of the second transistor and a bias voltage node.

6 . The interleaved sampling circuit of claim 5 , wherein a gate of the third transistor is coupled to the main clock node, each of the plurality of sampling circuits further comprising a fourth transistor configured to receive a respective one of non-overlapping clock signals at the respective one of the non-overlapping clock output nodes.

7 . The interleaved sampling circuit of claim 5 , wherein each of the plurality of sampling circuits further comprises a fourth transistor coupled between the bias voltage node and an input voltage node for the sampling circuit.

8 . The interleaved sampling circuit of claim 5 , wherein each of the plurality of sampling circuits further comprises:
a fourth transistor coupled between the bias voltage node and a reference potential node; a capacitive element coupled between the boosted voltage node and the bias voltage node; and a fifth transistor coupled between the boosted voltage node and a voltage rail.

9 . The interleaved sampling circuit of claim 8 , wherein:
a gate of the fourth transistor is configured to receive a signal complementary to a main clock signal at the main clock node; each of the plurality of sampling circuits further comprises a sixth transistor coupled between the bias voltage node and the reference potential node; and a gate of the sixth transistor is configured to receive a signal complementary to a respective one of non-overlapping clock signals at the respective one of the non-overlapping clock output nodes.

10 . The interleaved sampling circuit of claim 8 , further comprising a voltage doubler circuit having an output coupled to a gate of the fifth transistor.

11 . The interleaved sampling circuit of claim 8 , wherein a gate of the fifth transistor is coupled to the control input of the sampling switch.

12 . The interleaved sampling circuit of claim 1 , wherein each of the plurality of sampling circuits further comprises a NAND gate having a first input coupled to the main clock node and a second input coupled to the respective one of the non-overlapping clock output nodes, an output of the NAND gate being coupled to a gate of the first transistor.

13 . An interleaved sampling circuit, comprising:
a clock generator configured to generate non-overlapping clock signals based on a main clock signal; and a plurality of sampling circuits, each of the plurality of sampling circuits being configured to:
receive a respective one of the non-overlapping clock signals and the main clock signal;
select a portion of the main clock signal to be used as a sampling edge based on the respective one of the non-overlapping clock signals; and
sample an input voltage based on the respective one of the non-overlapping clock signals and the main clock signal, wherein the input voltage is sampled based on the sampling edge.

14 . The interleaved sampling circuit of claim 13 , wherein the non-overlapping clock signals have non-overlapping pulses.

15 . The interleaved sampling circuit of claim 13 , wherein a rising edge and a falling edge of a respective one of the non-overlapping clock signals occur at different times than a rising edge and a falling edge of the main clock signal.

16 . The interleaved sampling circuit of claim 13 , wherein each of the plurality of sampling circuits comprises:
a first transistor having a gate configured to receive the main clock signal and a drain coupled to an output clock node; and a sampling switch having a control input coupled to the output clock node.

17 . The interleaved sampling circuit of claim 16 , wherein each of the plurality of sampling circuits further comprises:
a capacitive element coupled to the sampling switch; and a quantizer coupled to the capacitive element.

18 . The interleaved sampling circuit of claim 16 , wherein each of the plurality of sampling circuits further comprises a second transistor having a gate configured to receive a signal complementary to the respective one of the non-overlapping clock signals and a drain coupled to the output clock node.

19 . A method for interleaved sampling, comprising:
generating, via a clock generator, non-overlapping clock signals based on a main clock signal; receiving, via each of a plurality of sampling circuits, a respective one of the non-overlapping clock signals and the main clock signal; selecting a portion of the main clock signal to be used as a sampling edge based on the respective one of the non-overlapping clock signals; and sampling, via each of the plurality of sampling circuits, an input voltage based on the respective one of the non-overlapping clock signals and the main clock signal, wherein the input voltage is sampled based on the sampling edge.

Assignees

• Qualcomm Inc

Inventors

• Sun Lei
• Sedighi Behnam
• Ji Honghao

Classifications

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03K17/56 Primary

  by the use, as active elements, of semiconductor devices (using diodes H03K17/74) · CPC title