Circuit for removing offset output voltage, and electronic device comprising same

Patent metadata

Field	Value
Publication number	US-12525938-B2
Application number	US-202118268475-A
Country	US
Kind code	B2
Filing date	Nov 16, 2021
Priority date	Feb 2, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

According to the present disclosure, a circuit for cancelling an off-set voltage included in an output voltage of an electronic component includes: a first resistor having one end connected to a bias voltage terminal; a second resistor connected to the first resistor, and having one end connected to the bias voltage terminal; a third resistor having one end connected to the first resistor and the other end connected to a ground terminal; and a transistor having one end connected to the second resistor and the other end connected to the ground terminal, and applied with an output voltage including an off-set voltage from a sensor.

First claim

What is claimed is:

1 . A circuit for cancelling an off-set voltage included in an output voltage of an electronic component, the circuit comprising:
a first resistor having one end connected to a bias voltage terminal; a second resistor connected to the first resistor, and having one end connected to the bias voltage terminal; a third resistor having one end connected to the first resistor and the other end connected to a ground terminal; and a transistor having one end connected to the second resistor and the other end connected to the ground terminal, and applied with an output voltage including the off-set voltage from a sensor.

2 . The circuit for cancelling an off-set output voltage according to claim 1 , wherein a first output terminal is connected between the first resistor and the third resistor,
a second output terminal is connected between the second resistor and the transistor, and an output voltage difference between the first output terminal and the second output terminal is 0.

3 . The circuit for cancelling an off-set output voltage according to claim 2 , wherein as a resistance value of the third resistor is varied, the output voltage difference between the first output terminal and the second output terminal is controlled to 0.

4 . The circuit for cancelling an off-set output voltage according to claim 3 , wherein the output voltage difference between the first output terminal and the second output terminal is enabled to be expressed as an Equation regarding a voltage value of the bias voltage terminal, respective resistance values of the first to third resistors, and a channel resistance value of the transistor.

5 . The circuit for cancelling an off-set output voltage according to claim 4 , wherein the equation is

V
A

-

V
B

=

V
CC

·

(

R
3

R
1

+

R
3

-

R

JFET
,

B
=

0
⁢
T

R

JFET
,

B
=

0
⁢
T

+

R
2

)

,

where V A represents an output voltage value of the first output terminal, V B represents the output voltage value of the second output terminal, V CC represent the voltage value of the bias voltage terminal, R 1 , R 2 , and R 3 represent the resistance values of the first to third resistors, respectively, and R JFET represents the channel resistance value of the transistor.

6 . The circuit for cancelling an off-set output voltage according to claim 5 , wherein the transistor is a junction gate field effect transistor (JFET).

7 . An electronic device comprising a circuit for cancelling an off-set voltage included in an output voltage of a hall sensor,
wherein the circuit includes a first resistor having one end connected to a bias voltage terminal; a second resistor connected to the first resistor in series, and having one end connected to the bias voltage terminal; a third resistor having one end connected to the first resistor and the other end connected to a ground terminal; and a transistor having one end connected to the second resistor and the other end connected to the ground terminal, and applied with an output voltage including the off-set voltage from the hall sensor.

8 . The electronic device according to claim 7 , wherein a first output terminal is connected between the first resistor and the third resistor,
a second output terminal is connected between the second resistor and the transistor, an output voltage difference between the first output terminal and the second output terminal is 0.

9 . The electronic device according to claim 8 , wherein as a resistance value of the third resistor is varied, the output voltage difference between the first output terminal and the second output terminal is controlled to 0.

10 . The electronic device according to claim 9 , wherein the output voltage difference between the first output terminal and the second output terminal is enabled to be expressed as an Equation regarding a voltage value of the bias voltage terminal, respective resistance values of the first to third resistors, and a channel resistance value of the transistor.

11 . The electronic device according to claim 10 , wherein the equation is

V
A

-

V
B

=

V
CC

·

(

R
3

R
1

+

R
3

-

R

JFET
,

B

Assignees

• Univ Chung Ang Ind Acad Coop Found

Inventors

• Song Sang Hun

Classifications

• H03F2200/261

  Amplifier which being suitable for instrumentation applications · CPC title

• H03F1/306 Primary

  in junction-FET amplifiers (H03F1/303, H03F1/305, H03F1/309 take precedence) · CPC title

• H03F2200/372

  Noise reduction and elimination in amplifier · CPC title

• H03F3/187

  in integrated circuits · CPC title

• G01R33/0029

  Treating the measured signals, e.g. removing offset or noise · CPC title