Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12525191-B2
Application number	US-202117778916-A
Country	US
Kind code	B2
Filing date	Jun 18, 2021
Priority date	Jun 18, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

The embodiments of the present disclosure provides a display substrate, including: an active region and a peripheral region, the active region is provided therein with a plurality of pixel units arranged in an array, all the pixel units are divided into n pixel unit groups, the peripheral region is provided therein with a driver block including a first gate drive circuit having n+x first signal output terminals configured to sequentially output first gate drive signals in an active level and the first gate line provided for an ith pixel unit group is electrically connected to a (i+x)th first signal output terminal, and the reset signal line provided for the ith pixel unit group is electrically connected to an ith first signal output terminal, with i being a positive integer and i≤n.

First claim

What is claimed is:

1 . A display substrate, comprising: an active region and a peripheral region surrounding the active region, wherein the active region is provided therein with a plurality of pixel units arranged in an array, all of the plurality of pixel units are divided into n pixel unit groups, each of the n pixel unit groups is provided with a corresponding first gate line and a corresponding reset signal line, the peripheral region is provided therein with a driver block comprising a first gate drive circuit, and the first gate drive circuit comprises (n+x) first signal output terminals configured to sequentially output first gate drive signals in an active level, with both n and x being positive integers, and x≥2; wherein
the first gate line for controlling writing of a data voltage to each pixel unit in an i th pixel unit group is electrically connected to a (i+x) th first signal output terminal, and the reset signal line for controlling writing of a reset voltage to each pixel unit in the i th pixel unit group is electrically connected to an i th first signal output terminal of (n+x) first signal output terminals, with i being a positive integer and i≤n,
the first gate drive circuit comprises (n+x) cascaded first shift registers, and a signal output terminal of the first shift register in a (x+i) th stage is a (x+i) th first signal output terminal, with i being a positive integer and i≤n,
among the (n+x) first signal output terminals of the first gate drive circuit, the (x+i) th first signal output terminal of the first shift register in the (x+i) th stage is respectively connected to the reset signal line of each pixel unit in the (x+i) th pixel unit group for controlling writing, via the reset signal line, of the reset voltage to the pixel unit in the (x+i) th pixel unit group and connected to the first gate line of each pixel unit in the i th pixel unit group for controlling writing, via the first gate line, of the data voltage to the pixel unit in the i th pixel unit group, with i being a positive integer, i≤n, and x≥2.

2 . The display substrate of claim 1 , wherein the display substrate comprises two driver blocks respectively located on opposite sides of the active region, or
the pixel units in a same row are located in a same pixel unit group, and the pixel units in different rows are located in different pixel unit groups.

3 . A display device, comprising: the display substrate of claim 1 .

4 . The display substrate of claim 1 , wherein each of the n pixel unit groups is provided with a corresponding second gate line, and the driver block further comprises a second gate drive circuit, the second gate drive circuit comprises n/a second signal output terminals configured to sequentially output second gate drive signals in an active level, with a being a positive integer, a<n, and n/a being a positive integer; and
the second gate line provided for the i th pixel unit group is electrically connected to a [i/a] th second signal output terminal, with [i/a] representing rounding up an operation result of i/a.

5 . The display substrate of claim 4 , wherein the second gate drive circuit comprises: n/a cascaded second shift registers, and
a signal output terminal of the second shift register in a k th stage is a k th second signal output terminal, with k being a positive integer and k<n/a.

6 . The display substrate of claim 5 , wherein an interval between a time when one of two adjacent first signal output terminals starts to output the first gate drive signal in an active level and a time when the other one of the two adjacent first signal output terminals successively starts to output the first gate drive signal in an active level is H, and an interval between a time when one of two adjacent second signal output terminals starts to output the second gate drive signal in an active level and a time when the other one of the two adjacent second signal output terminals successively starts to output the second gate drive signal in an active level is a*H; and
the first gate drive signal is a monopulse signal, and duration when the first gate drive signal is in an active level duirng one period is t, and H>t.

7 . The display substrate of claim 6 , wherein, in a same frame, a time period during which the second gate drive signal output by the k th second signal output terminal is in an active level at least partially overlaps with a time period during which the first gate drive signal output by each of a (a*k−a+1) th first signal output terminal to a (a*k) th first signal output terminal is in an active level, and also at least partially overlaps with a time period during which the first gate drive signal output by each of a (a*k−a+1+x) th first signal output terminal to a (a*k+x) th first signal output terminal is in an active level.

8 . The display substrate of claim 7 , wherein
in a same frame, a time when the k th second signal output terminal starts to output the second gate drive signal in an active level is prior to a time when the (a*k−a+1) th first signal output terminal starts to output the first gate drive signal in an active level, or in a same frame, a time when the k th second signal output terminal starts to output the second gate drive signal in an active level is the same as the time when the (a*k−a+1) th first signal output terminal starts to output the first gate drive signal in an active level.

9 . The display substrate of claim 8 , wherein the second gate drive signal is a monopulse signal during a frame; and
duration when the second gate drive signal is in an active level during one period is (x+a)*H.

10 . The display substrate of claim 8 , wherein the second gate drive signal is a double-pulse signal during a frame;
in one period, the double-pulse signal comprises a first part in an active level, a second part in an inactive level and a third part in an active level, with the second part being between the first part and the third part; in a same frame, a time period corresponding to the first part of the second gate drive signal output by the k th second signal output terminal at least partially overlaps with the time period during which the first gate drive signal output by each of the (a*k−a+1) th first signal output terminal to the (a*k) th first signal output terminal is in an active level; and a time period corresponding to the third part of the second gate drive signal output by the k th second signal output terminal at least partially overlaps with the time period during which the first gate drive signal output by each of the (a*k−a+1+x) th first signal output terminal to the (a*k+x) th first signal output terminal is in an active level.

11 . The display substrate of claim 10 , wherein duration of each of the first part and the third part is greater than or equal to a*H,
a value of a is 2, x>4, and the duration of each of the first part and the third part is 3H.

12 . The display substrate of claim 1 , wherein each of the pixel unit groups is provided with a corresponding light emission control line, the driver block further comprises: a light emission control drive circuit having n/b third signal output terminals configured to sequentially output light emission control signals in an active level, with b being a positive integer, b<n, and n/b being a positive integer; and
the light emission control line provided for the i th pixel unit group is electrically connected to a [i/b] th third signal output terminal, with [i/b] representing rounding up an operation result of i/b.

13 . The display substrate of claim 12 , wherein the light emission control drive circ

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shang Guangliang
• Liu Libin
• Wen Mengyang
• Lu Jiangnan
• Wang Li
• Han Long

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0257

  Reduction of after-image effects · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title