Gamma reference voltage output circuit and display device including the same

Patent metadata

Field	Value
Publication number	US-12525167-B2
Application number	US-202418938091-A
Country	US
Kind code	B2
Filing date	Nov 5, 2024
Priority date	Dec 6, 2023
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

Discussed are a gamma reference voltage output circuit and a display device. The gamma reference voltage output circuit includes an (N)th operational amplifier configured to output an (N)th gamma reference voltage through an (N)th output terminal, where N is a natural number, an (N+1)th operational amplifier configured to output an (N+1)th gamma reference voltage being lower than the (N)th gamma reference voltage through its (N+1)th output terminal, an (N+2)th operational amplifier configured to output an (N+2)th gamma reference voltage being lower than the (N+1)th gamma reference voltage to an (N+2)th output terminal, and one or more connection nodes to which a power terminal of one of adjacent operational amplifiers in the (N)th operational amplifier, the (N+1)th operational amplifier, and the (N+2)th operational amplifier is connected to an output terminal of another operational amplifier.

First claim

What is claimed is:

1 . A gamma reference voltage output circuit comprising:
an (N)th operational amplifier configured to output an (N)th gamma reference voltage through an (N)th output terminal, where N is a natural number; an (N+1)th operational amplifier configured to output an (N+1)th gamma reference voltage that is lower than the (N)th gamma reference voltage, through an (N+1)th output terminal; an (N+2)th operational amplifier configured to output an (N+2)th gamma reference voltage that is lower than the (N+1)th gamma reference voltage, to an (N+2)th output terminal; and at least one node to which a power terminal of one of adjacent operational amplifiers among the (N)th operational amplifier, the (N+1)th operational amplifier, and the (N+2)th operational amplifier is electrically connected to an output terminal of another operational amplifier.

2 . The gamma reference voltage output circuit of claim 1 , wherein
each of the (N)th operational amplifier, the (N+1)th operational amplifier, and the (N+2)th operational amplifier includes a first power terminal and a second power terminal, and the at least one node includes:
a first connection node configured to connect the (N)th output terminal to the first power terminal of the (N+1)th operational amplifier; and
a second connection node configured to connect the (N+1)th output terminal to the first power terminal of the (N+2)th operational amplifier.

3 . The gamma reference voltage output circuit of claim 2 , wherein
a driving voltage is applied to the first power terminal of the (N)th operational amplifier, a ground voltage is applied to the second power terminal of the (N)th operational amplifier, and the ground voltage is applied to the second power terminal of the (N+2)th operational amplifier.

4 . The gamma reference voltage output circuit of claim 3 , wherein the (N)th operational amplifier further includes:
a first transistor connected between the first power terminal and the (N)th output terminal of the (N)th operational amplifier; a second transistor connected between the (N)th output terminal, and the second power terminal of the (N)th operational amplifier; a control part configured to control a gate voltage of each of the first transistor of the (N)th operational amplifier and the second transistor of the (N)th operational amplifier; a first sensing part configured to sense a current flowing through the first transistor of the (N)th operational amplifier; and a second sensing part configured to sense a current flowing through the second transistor of the (N)th operational amplifier.

5 . The gamma reference voltage output circuit of claim 3 , wherein the (N+1)th operational amplifier further includes:
a first transistor connected between the first power terminal and the (N+1)th output terminal of the (N+1)th operational amplifier; a second transistor connected between the (N+1)th output terminal, and the second power terminal of the (N+1)th operational amplifier; a control part configured to control a gate voltage of each of the first transistor of the (N+1)th operational amplifier and the second transistor of the (N+1)th operational amplifier; and a sensing part configured to sense a current flowing through the second transistor of the (N+1)th operational amplifier, and wherein the (N+2)th operational amplifier further includes:
a first transistor connected between the first power terminal and the (N+2)th output terminal of the (N+2)th operational amplifier;
a second transistor connected between the (N+2)th output terminal, and the second power terminal of the (N+2)th operational amplifier;
a control part configured to control a gate voltage of each of the first transistor of the (N+2)th operational amplifier and the second transistor of the (N+2)th operational amplifier; and
a sensing part configured to sense a current flowing through the second transistor of the (N+2)th operational amplifier.

6 . The gamma reference voltage output circuit of claim 1 , wherein
each of the (N)th operational amplifier, the (N+1)th operational amplifier, and the (N+2) operational amplifier includes a first power terminal and a second power terminal, and the at least one connection node includes:
a first connection node configured to connect the second power terminal of the (N)th operational amplifier to the (N+1)th output terminal; and
a second connection node configured to connect the second power terminal of the (N+1)th operational amplifier to the (N+2)th output terminal.

7 . The gamma reference voltage output circuit of claim 6 , wherein a driving voltage is applied to the first power terminal of the (N)th operational amplifier;
a ground voltage is applied to the second power terminal of the (N+2)th operational amplifier.

8 . The gamma reference voltage output circuit of claim 7 , wherein the (N)th operational amplifier further includes:
a first transistor connected between the first power terminal and the (N)th output terminal of the (N)th operational amplifier; a second transistor connected between the (N)th output terminal, and the second power terminal of the (N)th operational amplifier; a control part configured to control a gate voltage of each of the first transistor of the (N)th operational amplifier and the second transistor of the (N)th operational amplifier; and a sensing part configured to sense a current flowing through the first transistor of the (N)th operational amplifier, and wherein the (N+1)th operational amplifier further includes:
a first transistor connected between the first power terminal and the (N+1)th output terminal of the (N+1)th operational amplifier;
a second transistor connected between the (N+1)th output terminal, and the second power terminal of the (N+1)th operational amplifier;
a control part configured to control a gate voltage of each of the first transistor of the (N+1)th operational amplifier and the second transistor of the (N+1)th operational amplifier; and
a sensing part configured to sense a current flowing through the first transistor of the (N+1)th operational amplifier.

9 . The gamma reference voltage output circuit of claim 7 , wherein the (N+2)th operational amplifier further includes:
a first transistor connected between the first power terminal and the (N+2)th output terminal of the (N+2)th operational amplifier; a second transistor connected between the (N+2)th output terminal, and the second power terminal of the (N+2)th operational amplifier; a control part configured to control a gate voltage of each of the first transistor of the (N+2)th operational amplifier and the second transistor of the (N+2)th operational amplifier; a first sensing part configured to sense a current flowing through the first transistor of the (N+2)th operational amplifier; and a second sensing part configured to sense a current flowing through the second transistor of the (N+2)th operational amplifier.

10 . The gamma reference voltage output circuit of claim 1 , wherein each of the (N)th operational amplifier, the (N+1)th operational amplifier, and the (N+2) operational amplifier includes a first power terminal and a second power terminal, and
wherein the at least one connection node includes:
a first-first connection node configured to connect the (N)th output terminal to the first power terminal of the (N+1)th operational amplifier;
a first-second connection node configured to connect the (N+1)th output terminal to the first power terminal of the (N+2) operational amplifier;
a second-first connection node configured to connect the second power terminal of the (N)th operational amplifier to the (N+1)th output terminal; and
a second-second connec

Assignees

• Lg Display Co Ltd

Inventors

• Han Jae Won
• Kim Jung Jae
• Park Min Gyu

Classifications

• G09G2310/027

  Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title

• G09G2330/025

  Reduction of instantaneous peaks of current · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2330/12

  Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

• G09G2330/028

  Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title