Display panel and display device including the same

Patent metadata

Field	Value
Publication number	US-12525166-B2
Application number	US-202418790972-A
Country	US
Kind code	B2
Filing date	Jul 31, 2024
Priority date	Sep 17, 2021
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

The present disclosure provides a display panel and a display device including the same. In the display panel, panel defects caused by static electricity induced due to an MPS line remaining on the panel after a cutting process in a cell array process of a display device is removed, the remaining MPS line is electrically connected to an ESD circuit through a discharge line, thus the static electricity induced by the MPS line remaining in the panel flows to the ESD circuit through the discharge line, thereby suppressing the panel defects caused by the MPS line.

First claim

What is claimed is:

1 . A display device comprising:
a display panel obtained by just-cutting a parent panel having a plurality of panel areas arranged adjacent to one another in a scribe process, wherein the display panel includes: a base substrate including a display area and a non-display area disposed outside of the display area, and a pixel defined in each of intersections between a plurality of gate lines and a plurality of data lines in the display area; a multi-pattern search (MPS) area disposed in an upper area of the non-display area, wherein at least one MPS line is disposed in the MPS area; an electrostatic discharge (ESD) area in which at least one ESD circuit is disposed, wherein the at least one ESD circuit discharges static electricity generated in the display area and the non-display area; a ground area between the MPS area and the ESD area, wherein a ground electrode is disposed in the ground area; a static electricity discharge part including at least one discharge line for connecting the at least one MPS line to the at least one ESD circuit, wherein the at least one discharge line overlaps the ground electrode in the ground area; and a gate in panel (GIP) for supplying a scan signal to the plurality of gate lines; and a data driver for supplying a data signal to the plurality of data lines.

2 . The display panel of claim 1 , wherein the at least one discharge line is connected at one end to the at least one MPS line, extends through the ground area to overlap the ground electrode, and is connected at another end to the at least one ESD circuit.

3 . The display panel of claim 1 , wherein the at least one ESD circuit comprises at least one discharge ESD circuit connected at one end to the at least one discharge line and connected at another end to the ground electrode.

4 . The display panel of claim 1 , wherein the at least one ESD circuit comprises at least one thin-film transistor connected at one end to the at least one discharge line and connected at another end to the ground electrode.

5 . A display panel comprising:
a display area configured to display images; a non-display area disposed outside the display area; a multi-pattern search MPS area including a plurality of MPS lines configured to check disconnection and short circuit of each signal line of a thin-film transistor array in the display area; an electrostatic discharge ESD area including a plurality of discharging ESD circuits configured to discharge static electricity generated in the display area and the non-display area and a plurality of redundant ESD circuits configured to maintain a constant spacing among the plurality of discharging ESD circuits; a ground area including a ground electrode disposed between the MPS area and the ESD area, and connected to the plurality of discharging ESD circuits through a ground connection line; and a plurality of discharge lines electrically connecting the plurality of MPS lines and the plurality of ESD circuits and connected to the ground electrode.

6 . The display panel of claim 5 , wherein the ESD area further includes a plurality of pixel ESD circuit connected to each pixel of the display area and the ground electrode.

7 . The display panel of claim 5 , further comprising a common voltage line disposed between the ESD area and the display area and connected with each pixel of the display area.

8 . The display panel of claim 5 , wherein the plurality of discharge lines are formed of a transparent conductive material.

9 . The display panel of claim 5 , wherein the plurality of discharge lines are connected at one end to the plurality of MPS lines, extend through the ground area to overlap the ground electrode, and are connected at another end to the plurality of discharging ESD circuits.

10 . The display panel of claim 5 , wherein the plurality of redundant ESD circuits are configured to be connectable to the plurality of discharge lines.

Assignees

• Lg Display Co Ltd

Inventors

• Park Yangsu
• Jung Chanyong
• Kwon Taewook

Classifications

• G09G2330/04

  Display protection · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2330/08

  Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

• G09G2330/025

  Reduction of instantaneous peaks of current · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title