Techniques for controlling computing performance for power-constrained multi-processor computing systems

US12524059B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12524059-B2
Application numberUS-202217961430-A
CountryUS
Kind codeB2
Filing dateOct 6, 2022
Priority dateJan 6, 2022
Publication dateJan 13, 2026
Grant dateJan 13, 2026

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  1. Title

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  2. Abstract

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A computer-implemented method of controlling power consumption in a multi-processor computing device comprises determining a first value for a first power setting associated with a first processor based on a sound level generated by the multi-processor computing device; determining a second value for the first power setting based on a power consumption level of the multi-processor computing device; comparing the first value to the second value; and causing the first processor to perform one or more operations based on the lesser of the first value and the second value.

First claim

Opening claim text (preview).

What is claimed is: 1 . A computer-implemented method of controlling power consumption in a multi-processor computing device, the method comprising: determining a first value for a first power setting associated with a first processor based on a target sound level for the multi-processor computing device; determining a second value for the first power setting associated with the first processor based on a target power consumption level of the multi- processor computing device; comparing the first value for the first power setting to the second value for the first power setting to determine a restrictive value for the first power setting comprising a lesser value of the first value and the second value; and causing the first processor to perform one or more operations based on the restrictive value for the first power setting. 2 . The computer-implemented method of claim 1 , wherein the first power setting comprises one of a frequency cap for the first processor during operation, or a frame-rate limit for the first processor during operation. 3 . The computer-implemented method of claim 1 , further comprising determining a first set of active cores associated with the first processor and a second set of inactive cores associated with the first processor. 4 . The computer-implemented method of claim 3 , wherein causing the first processor to perform one or more operations comprises causing the first processor to perform the one or more operations using the first set of active cores but not the second set of inactive cores. 5 . The computer-implemented method of claim 1 , further comprising determining that a total processor power associated with the multi-processor computing device is less than a threshold value. 6 . The computer-implemented method of claim 1 , wherein the target power consumption level of the multi-processor computing device comprises a sum of a first power level consumed by the first processor and a second power level consumed by a second processor of the multi-processor computing device. 7 . The computer-implemented method of claim 1 , wherein determining the first value for the first power setting comprises determining whether a current sound level generated by a first fan associated with the first processor and a second fan associated with a second processor of the multi-processor computing device exceeds the target sound level. 8 . The computer-implemented method of claim 7 , wherein the target sound level is based on one or more candidate fan speed combinations determined for the first fan and the second fan. 9 . The computer-implemented method of claim 7 , wherein determining the first value for the first power setting comprises: determining one or more candidate fan speed combinations for the first fan and the second fan; and computing a temperature error for a temperature-controlled device included in the multi-processor computing device based on the one or more candidate fan speed combinations and a measured temperature value associated with the temperature-controlled device. 10 . The computer-implemented method of claim 1 , wherein determining the first value for the first power setting is based on a temperature error associated with one of the first processor, a second processor of the multi-processor computing device, or a temperature-controlled device included in the multi-processor computing device. 11 . The computer-implemented method of claim 1 , wherein the restrictive value for the first power setting causes the first processor to execute at a highest performance level that complies with the target sound level and the target power consumption level. 12 . A non-transitory computer readable medium storing instructions that, when executed by a processor, cause the processor to perform the steps of: determining a first value for a first power setting associated with a first processor of a multi-processor computing device based on a target sound level for the multi-processor computing device; determining a second value for the first power setting associated with the first processor based on a target power consumption level of the multi- processor computing device; comparing the first value for the first power setting to the second value for the first power setting to determine a restrictive value for the first power setting comprising a lesser value of the first value and the second value; and causing the first processor to perform one or more operations based on the restrictive value for the first power setting. 13 . The non-transitory computer readable medium of claim 12 , wherein the first power setting comprises one of a frequency cap for the first processor during operation or a frame-rate limit for the first processor during operation. 14 . The non-transitory computer readable medium of claim 12 , wherein the steps further comprise determining a first set of active cores associated with the first processor and a second set of inactive cores associated with the first processor. 15 . The non-transitory computer readable medium of claim 14 , wherein causing the first processor to perform one or more operations comprises causing the first processor to perform the one or more operations using the first set of active cores but not the second set of inactive cores. 16 . The non-transitory computer readable medium of claim 14 , wherein the steps further comprise determining that a total processor power associated with the multi-processor computing device is less than a threshold value. 17 . The non-transitory computer readable medium of claim 12 , wherein the target power consumption level of the multi-processor computing device comprises a sum of a first power level consumed by the first processor and a second power level consumed by a second processor of the multi-processor computing device. 18 . The non-transitory computer readable medium of claim 12 , wherein determining the first value for the first power setting comprises determining whether a current sound level generated by a first fan associated with the first processor and a second fan associated with a second processor of the multi-processor computing device exceeds the target sound level. 19 . The non-transitory computer readable medium of claim 18 , wherein determining the first value for the first power setting comprises: determining one or more candidate fan speed combinations for the first fan and the second fan; and computing a temperature error for a temperature-controlled device included in the multi-processor computing device based on the one or more candidate fan speed combinations and a measured temperature value associated with the temperature-controlled device. 20 . The non-transitory computer readable medium of claim 12 , wherein the steps further comprise determining a first value for a second power setting associated with a second processor based on an error rate associated with a plurality of computational tasks provisioned by the second processor and a plurality of computational tasks completed by the first processor. 21 . A system, comprising: a memory that stores instructions; and a processor that is communicatively coupled to the memory and is configured to, when executing the instructions, perform the steps of: determining a first value for a first power setting associated with a first processor of a multi-processor computing device based on a target sound level for the multi-processor computing device; determining a second value for the fi

Assignees

Inventors

Classifications

  • using expert systems only · CPC title

  • by switching off individual functional units in the computer system · CPC title

  • by lowering clock frequency · CPC title

  • Cooling means · CPC title

  • G06F1/206Primary

    comprising thermal management · CPC title

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What does patent US12524059B2 cover?
A computer-implemented method of controlling power consumption in a multi-processor computing device comprises determining a first value for a first power setting associated with a first processor based on a sound level generated by the multi-processor computing device; determining a second value for the first power setting based on a power consumption level of the multi-processor computing dev…
Who is the assignee on this patent?
Nvidia Corp
What technology area does this patent fall under?
Primary CPC classification G06F1/206. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 13 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).