Method for setting of semiconductor manufacturing parameter and computing device for executing the method

Patent metadata

Field	Value
Publication number	US-12523938-B2
Application number	US-202117551450-A
Country	US
Kind code	B2
Filing date	Dec 15, 2021
Priority date	Oct 15, 2020
Publication date	Jan 13, 2026
Grant date	Jan 13, 2026

Abstract

A method for setting of a semiconductor manufacturing parameter according to an embodiment is a method performed in a computing device including one or more processors, and a memory for storing one or more programs executed by the one or more processors, the method including an operation of inputting manufacturing parameters for manufacturing a semiconductor to a neural network model and an operation of training the neural network model to predict at least one of power and delay of the semiconductor based on the input manufacturing parameters.

First claim

What is claimed is:

1 . A method for setting of a semiconductor manufacturing parameter performed in a computing device comprising one or more processors and a memory for storing one or more programs executed by the one or more processors, the method comprising:
an operation of inputting manufacturing parameters for manufacturing a semiconductor to a neural network model; and an operation of training the neural network model to predict at least one of power and delay of the semiconductor based on the input manufacturing parameters, wherein the operation of training the neural network model trains the neural network model to predict at least one of the power and delay of the semiconductor within a range of a preset minimum value to maximum value for each of the manufacturing parameters, wherein the neural network model comprises:
a first neural network model configured to receive each manufacturing parameter and is trained to predict the power of the semiconductor from each received manufacturing parameter; and
a second neural network model configured to receive each manufacturing parameter and is trained to predict the delay of the semiconductor from each received manufacturing parameter,
wherein the operation of inputting into the neural network model inputs a value obtained by taking a log of the manufacturing parameters to the neural network model; and loss functions of the first neural network model and the second neural network model is represented by Equation 1 below:

L
y

=

1
N

⁢

∑
i
N

⁢



log
⁡

(

O
y
i

)

-

log
⁡

(

D
y
i

)



2

,

y
=

power
⁢

⁢
or
⁢

⁢
delay

[

Equation
⁢

⁢
1

]

where L y : loss function of the first neural network model when y=power, loss function of the second neural network model when y=delay;
N: the number of training data of the first neural network model and the second neural network model;
i: i-th training data;
log(O y i ): predicted value of the first neural network model (when y=power) and the second neural network model (when y=delay) for the i-th training data; and
log (D y i ): target value of the first neural network model (when y=power) and the second neural network model (when y=delay) for the i-th training data.

2 . The method of claim 1 , wherein the operation of inputting into the neural network model inputs a value obtained by taking a log of the manufacturing parameters to the neural network model.

3 . The method of claim 1 , wherein the neural network model is trained to predict each of the power and the delay of the semiconductor from each inputted manufacturing parameter; and
the method for setting of the semiconductor manufacturing parameter further comprises an operation of calculating power delay products (PDP) based on the power and the delay predicted by the neural network model.

4 . The method of claim 3 , wherein the method for setting of the semiconductor manufacturing parameter further comprises an operation of extracting values of manufacturing parameters that minimize the PDP by using the trained neural network model.

5 . The method of claim 4 , wherein the operation of extracting the values of the manufacturing parameters that minimize the PDP extracts values of the manufacturing parameters that minimize the PDP by applying a gradient descent method to the trained neural network model.

6 . The method of claim 5 , wherein the operation of extracting the values of the manufacturing parameters that minimize the PDP by applying the gradient descent method comprises:
an operation of setting an initial value of each manufacturing parameter and a learning rate of the neural network model; an operation of calculating a slope of the PDP with respect to the initial value of the manufacturing parameter and updating the manufacturing parameter for moving the slope of the PDP in a negative direction using the learning rate; and an operation of repeating the operation of updating until a preset interruption condition is satisfied.

7 . The method of claim 6 , wherein the operation of inputting to the neural network model inputs the value obtained by taking a log of the manufacturing parameters to the neural network model; and
a slope G(x) of the PDP is calculated through Equation 2 below, and the update of the manufacturing parameter is performed through Equation 3 below:

G
⁡

(
x
)

=

d
⁡

(

log

Assignees

• Univ Yeungnam Res Cooperation Foundation
• Postech Res & Business Dev Found

Inventors

• Choi Hyun Chul
• Baek Rock Hyun
• Yoon Jun Sik
• Yun Hyeok

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06N3/049

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/0499

  Feedforward networks · CPC title

• G06N3/09

  Supervised learning · CPC title

• G03F7/705 Primary

  Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions · CPC title