Display panel

Patent metadata

Field	Value
Publication number	US-12520692-B2
Application number	US-202318324407-A
Country	US
Kind code	B2
Filing date	May 26, 2023
Priority date	Jan 29, 2021
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A display panel includes: a substrate; a plurality of pixel units arranged in an array along a first direction and a second direction intersecting each other, each of the pixel units includes N sub-pixels; and a plurality of pixel circuit units, each of the pixel circuit units includes N pixel circuits, each of the pixel circuit units is provided with at least one arrangement unit, and in the arrangement unit, M pixel circuits are arranged adjacently in sequence, in which an orthographic projection of the at least one arrangement unit of each of the pixel circuit units on the substrate overlaps an orthographic projection of P sub-pixels of a corresponding one of the pixel units on the substrate, and P is an integer greater than or equal to 1 and less than N.

First claim

What is claimed is:

1 . A display panel, comprising:
a substrate; a plurality of pixel units arranged on the substrate in an array along a first direction and a second direction intersecting each other, each pixel unit of the plurality of pixel units comprising N sub-pixels, N being an integer greater than or equal to 3, wherein the N sub-pixels of each pixel unit of the plurality of pixel units further comprise:
a first color sub-pixel;
a second color sub-pixel; and
a third color sub-pixel, a light-emitting area of the third color sub-pixel is less than a light-emitting area of the first color sub-pixel and less than a light-emitting area of the second color sub-pixel; and
a plurality of pixel circuit units arranged on the substrate, each pixel circuit unit of the plurality of pixel circuit units comprises:
N pixel circuits, each pixel circuit of the N pixel circuits being electrically connected to a corresponding one of the N sub-pixels, each pixel circuit unit of the plurality of pixel circuit units being provided with a first arrangement unit and a second arrangement unit, an orthographic projection of the first arrangement unit on the substrate overlaps the first color sub-pixel, and an orthographic projection of the second arrangement unit on the substrate overlaps the second color sub-pixel, and, in each arrangement unit, M pixel circuits being arranged adjacently in sequence, M being an integer greater than or equal to 2 and less than or equal to N, wherein an orthographic projection of all arrangement units of each pixel circuit unit of the plurality of pixel circuit units on the substrate overlaps an orthographic projection of P sub-pixels of a corresponding pixel unit of the plurality of pixel units on the substrate, and P is an integer greater than or equal to 1 and less than N.

2 . The display panel of claim 1 , wherein an orthographic projection of all arrangement units on the substrate overlaps an orthographic projection of the first color sub-pixel and the second color sub-pixel on the substrate.

3 . The display panel of claim 1 , wherein at least two arrangement units are adjacent, the adjacent arrangement units are connected with wires, and the wires are light-transmitting wires.

4 . The display panel of claim 1 , wherein at least two arrangement units are adjacent, the adjacent arrangement units are connected with wires, each of the wires comprises a first conductor layer and a second conductor layer stacked in a direction perpendicular to the substrate, a resistivity of the first conductor layer is less than a resistivity of the second conductor layer, a light transmittance of the second conductor layer is greater than a light transmittance of the first conductor layer, and an orthographic projection of the first conductor layer on the substrate is within an orthographic projection of the second conductor layer on the substrate.

5 . The display panel of claim 1 , wherein, in at least two arrangement units, the N pixel circuits is arranged in an array along the first direction and the second direction.

6 . The display panel of claim 1 , wherein the plurality of pixel circuit units is arranged in a plurality of rows and columns,
in each row of the plurality of pixel circuit units, the plurality of pixel circuit units is arranged along the first direction, and, in each column of the plurality of pixel circuit units, the plurality of pixel circuit units is arranged along the second direction, and the display panel further comprises: a plurality of first signal lines, each first signal line of the plurality of first signal lines being connected to a row of the plurality of pixel circuit units, each first signal line comprising: a first line segment and a second line segment, an orthographic projection of the first line segment on the substrate being within an orthographic projection of the pixel circuit on the substrate, the second line segment being connected between adjacent pixel circuit units, and an extension direction of at least one second line segment being tilted with respect to the first direction.

7 . The display panel of claim 6 , wherein each first signal line of the plurality of first signal lines further comprises:
a third line segment being connected between adjacent arrangement units in each pixel circuit unit, and an extension direction of at least one third line segment is tilted with respect to both of the first direction and the second direction.

8 . The display panel of claim 6 , wherein extension directions of second line segments of adjacent first signal lines intersect.

9 . The display panel of claim 7 , wherein extension directions of third line segments of adjacent first signal lines intersect.

10 . The display panel of claim 1 , wherein the plurality of pixel circuit units is arranged in a plurality of rows and columns,
in each row of the plurality of pixel circuit units, the plurality of the pixel circuit units is arranged along the first direction, in each column of the plurality of pixel circuit units, the plurality of the pixel circuit units is arranged along the second direction, the display panel further comprises: a plurality of second signal line groups, each second signal line group of the plurality of second signal line groups is connected with a column of the pixel circuit units and further comprises: a plurality of second signal lines, each second signal line of the plurality of second signal lines further comprising: a fourth line segment and a fifth line segment, an orthographic projection of the fourth line segment on the substrate being within an orthographic projection of each pixel circuit on the substrate, the fifth line segment being connected between adjacent pixel circuit units, and at least two of the second signal lines being closer to each other at the fifth line segment than at the fourth line segment.

11 . The display panel of claim 1 , wherein the orthographic projection of the P sub-pixels on the substrate completely covers the orthographic projection of at least one arrangement unit of each pixel circuit unit of the plurality of pixel circuit units on the substrate.

12 . The display panel of claim 6 , wherein each first signal line of the plurality of first signal lines further comprises:
at least one of a scan signal line and a light-emitting signal line.

13 . The display panel of claim 10 , wherein each second signal line of the plurality of second signal lines further comprises:
at least one of a data signal line and a power supply signal line.

14 . The display panel of claim 6 , wherein extension directions of second line segments of adjacent first signal lines are parallel to each other.

15 . The display panel of claim 7 , wherein extension directions of third line segments of adjacent first signal lines are parallel to each other.

16 . The display panel of claim 1 , wherein each pixel circuit unit of the plurality of pixel circuit units includes four pixel circuits arranged adjacently in sequence.

17 . The display panel of claim 1 , wherein each pixel circuit unit of the plurality of pixel circuit units includes four pixel circuits which are arranged in a 2×2 layout.

18 . The display panel of claim 1 , further comprising:
two photosensitive components configured to capture external image information and perform optical fingerprint recognition.

Assignees

• Yungu Guan Tech Co Ltd

Inventors

• Li Hongrui
• Liu Rusheng
• Feng Hongqing
• Zhang Bing
• Gai Cuili

Classifications

• H10K59/82

  Interconnections, e.g. terminals (H10K59/131, H10K59/179 take precedence) · CPC title

• H05K2201/09227

  Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting · CPC title

• H05K1/0296

  Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295 (H05K1/11 takes precedence; lay-out adapted to mounted component configuration H05K1/18) · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• G09G2300/0439

  Pixel structures · CPC title