Display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-12520689-B2
Application number	US-202519068221-A
Country	US
Kind code	B2
Filing date	Mar 3, 2025
Priority date	Apr 23, 2021
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A display panel and a display apparatus are provided. The display panel includes pixel circuits, light-emitting devices, reset signal lines electrically connected to the pixel circuits, a first connection portion in a circuit region and each extending along a second direction, a substrate, and metal layers and a semiconductor layer. The reset signal lines extend along a first direction and include first reset signal lines in a first display region. The pixel circuits are electrically connected to the light-emitting devices. At least one first pixel circuit group is disposed in the circuit region, the first pixel circuit group includes at least two pixel circuits arranged along the second direction intersecting the first direction. The at least two pixel circuits are electrically connected to one first reset signal line through one first connection portion. The first connection portion is located in a same metal layer.

First claim

What is claimed is:

1 . A display panel, having a display region comprising a first display region and a second display region; the first display region comprising at least one circuit region and at least one wiring region; and the display panel comprising:
pixel circuits; light-emitting devices, wherein the pixel circuits are electrically connected to the light-emitting devices; reset signal lines electrically connected to the pixel circuits, wherein the reset signal lines extend along a first direction and comprise first reset signal lines located in the first display region; at least one first connection portion located in the at least one circuit region and each extending along a second direction; a substrate; and metal layers and a semiconductor layer that are located at a side of the substrate, wherein at least one first pixel circuit group is disposed in the at least one circuit region, wherein each of the at least one first pixel circuit group comprises at least two pixel circuits of the pixel circuits, and the at least two pixel circuits are arranged along the second direction intersecting the first direction; wherein the at least two pixel circuits in one first pixel circuit group of the at least one first pixel circuit group are electrically connected to one of the first reset signal lines through one of the at least one first connection portion; and wherein the at least one first connection portion is located in at least one metal layer of the metal layers.

2 . The display panel according to claim 1 , wherein each of the pixel circuits comprises a drive transistor and a first reset transistor, wherein a first electrode of the first reset transistor is electrically connected to a control terminal of the drive transistor;
wherein the first reset signal lines comprise at least one first reset signal sub-line; wherein the first connection portion comprises a first connection sub-portion; wherein second electrodes of the first reset transistors of the at least two pixel circuits in one of the first pixel circuit groups are electrically connected to one of the at least one first reset signal sub-line through the first connection sub-portion; wherein the display panel further comprises at least one first reset scan line, wherein control terminals of the first reset transistors in one of the at least one first pixel circuit group are electrically connected to one of the at least one first reset scan line; wherein, in the first display region, one of the at least one first reset scan line is electrically connected to at least two first pixel circuit group that are arranged along the second direction, and one of the at least one first reset signal sub-line is electrically connected to at least two first pixel circuit group that are arranged along the first direction; and wherein, in the at least one circuit region, one of the at least one first connection sub-portion is arranged at a side of one of the at least one first reset scan line away from the drive transistor.

3 . The display panel according to claim 2 , wherein each of the pixel circuits further comprises a second reset transistor, wherein the second reset transistor comprises a second electrode electrically connected to a first electrode of one of the light-emitting devices;
wherein the first reset signal lines further comprise at least one second reset signal sub-line; wherein the first connection portion further comprises a second connection sub-portion, and second electrodes of the second reset transistors of the at least two pixel circuits in one of the first pixel circuit groups are electrically connected to one of the at least one second reset signal sub-line through the second connection sub-portion; wherein the display panel further comprises at least one second reset scan line, wherein control terminals of the first reset transistors in one of the at least one first pixel circuit group are electrically connected to one of the at least one first reset scan line; wherein, in the first display region, one of the at least one second reset scan line is electrically connected to at least two first pixel circuit group that are arranged along the second direction, and one of the at least one second reset signal sub-line is electrically connected to at least two first pixel circuit group that are arranged along the first direction; and wherein, in the at least one circuit region, one of the at least one second connection sub-portion is arranged at a side of one of the at least one second reset scan line away from the drive transistor.

4 . The display panel according to claim 3 , wherein the first connection sub-portion and the second connection sub-portion are located in one of the metal layers.

5 . The display panel according to claim 4 , wherein the at least one first reset scan line and the at least one second reset scan line are located in one of the metal layers, and the first connection sub-portion and the at least one first reset scan line are located in different layers.

6 . The display panel according to claim 3 , wherein a reset signal provided by one of the at least one first reset signal sub-line has a voltage different from a voltage of a reset signal provided by one of the at least one second reset signal sub-line.

7 . The display panel according to claim 3 , wherein a reset signal provided by one of the at least one first reset signal sub-line has a voltage greater than a voltage of a reset signal provided by one of the at least one second reset signal sub-line.

8 . The display panel according to claim 1 , further comprising:
a data line and a power signal line, each of which extends along the first direction, wherein each of the pixel circuits further comprises a data writing transistor, wherein the data writing transistor comprises a first electrode electrically connected to the data line, and a second electrode electrically connected to a first electrode of the drive transistor; and wherein, in one of the at least one circuit region, the data line and the power signal line are at least partially located in different metal layers of the metal layers.

9 . The display panel according to claim 1 , wherein the metal layers comprise a first metal layer, a second metal layer, and a third metal layer, wherein the first metal layer is located on a side of the semiconductor layer away from the substrate, the second metal layer is located on a side of the first metal layer away from the substrate, and the third metal layer is located on a side of the second metal layer away from the substrate;
wherein each of the pixel circuits comprises a drive transistor and a storage capacitor, wherein the drive transistor comprises a channel located in the semiconductor layer, the storage capacitor comprises a first plate located in the first metal layer and a second plate located in the second metal layer, and the storage capacitor partially overlaps the channel of the drive transistor; wherein the at least one first reset signal sub-line is at least partially located in the third metal layer; and wherein the first connection sub-portion is located in the second metal layer.

10 . The display panel according to claim 9 , wherein the first metal layer and the second metal layer comprises molybdenum, and the third metal layer comprises one or more of titanium, aluminum, and molybdenum.

11 . The display panel according to claim 1 , further comprising:
at least one light-emitting device group comprising at least one first light-emitting device group, wherein one first light-emitting device group of the at least one first light-emitting device group comprises three light-emitting devices of the ligh

Assignees

• Wuhan Tianma Micro Electronics Co Ltd

Inventors

• Ma Yangzhao
• Wang Meihong
• Dai Hao
• Mu Pengcheng
• Li Lida

Classifications

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09G2340/0407

  Resolution change, inclusive of the use of different resolutions for different screen areas · CPC title