Display substrate including connection line and power line surrounding display area, preparation method thereof, and display device

Patent metadata

Field	Value
Publication number	US-12520684-B2
Application number	US-202418645403-A
Country	US
Kind code	B2
Filing date	Apr 25, 2024
Priority date	Feb 10, 2021
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A display substrate includes a display region and a peripheral region on a periphery of the display region. At least multiple sub-pixels are arranged in the display region. At least one sub-pixel includes a pixel driving circuit arranged on an underlay substrate and a light emitting element connected with the pixel driving circuit. The light emitting element includes an anode, a light emitting layer and a cathode, and the cathode is electrically connected with a first power line. The first power line and a signal connection line are arranged in the peripheral region. A first sub-power line is connected with the first power line through the signal connection line in the peripheral region, and the first sub-power line is arranged in the display region.

First claim

The invention claimed is:

1 . A display substrate, comprising:
a display region and a peripheral region on a periphery of the display region, wherein at least multiple sub-pixels are arranged in the display region, and at least one of the at least multiple sub-pixels comprises a pixel driving circuit arranged on an underlay substrate and a light emitting element connected with the pixel driving circuit; the light emitting element comprises an anode, a light emitting layer and a cathode, and the cathode is electrically connected with a first power line; and the first power line and a signal connection line are arranged in the peripheral region, and a first initial signal line is connected with the first power line through the signal connection line in the peripheral region; wherein the first initial signal line is arranged in the display region and along a row direction of the at least multiple sub-pixels; the signal connection line comprises a first connection line and a second connection line, and the first connection line and the second connection line extend along a column direction of the at least multiple sub-pixels; the second connection line is connected with the first initial signal line and connected with the first power line through the first connection line; the first connection line is on a side of the first power line away from the underlay substrate; the first initial signal line is on a side of the second connection line close to the underlay substrate, and the second connection line is on a side of the first initial signal line away from the underlay substrate; and an orthographic projection of the first connection line on the underlay substrate covers a portion of an orthographic projection of the second connection line on the underlay substrate and a portion of an orthographic projection of the first power line on the underlay substrate.

2 . The display substrate according to claim 1 , further comprising a light emitting driving circuit and a scan driving circuit in the peripheral region, the light emitting driving circuit and the scan driving circuit are located between the first power line and the display region, and the orthographic projection of the first connection line on the underlay substrate overlaps with an orthographic projection of at least one of the light emitting driving circuit and the scan driving circuit on the underlay substrate.

3 . The display substrate according to claim 2 , wherein the first connection line comprises at least multiple openings in a region in which the orthographic projection of the first connection line on the underlay substrate overlaps with the orthographic projection of the at least one of the light emitting driving circuit and the scan driving circuit on the underlay substrate.

4 . The display substrate according to claim 1 , wherein a width of the first connection line is greater than a width of the second connection line.

5 . The display substrate according to claim 1 , wherein the second connection line is in the same layer as the first power line.

6 . The display substrate according to claim 1 , wherein the extending direction of the first connection line in the peripheral region intersects with the extending direction of the first initial signal line in the display region.

7 . The display substrate according to claim 1 , wherein the display region comprises a driving structure layer and the light emitting element which are arranged on the underlay substrate, and the anode is on a side of the cathode close to the underlay substrate; and
the first connection line is in the same layer as the anode of the light emitting element.

8 . The display substrate according to claim 7 , wherein the driving structure layer comprises a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source and drain metal layer which are arranged on the underlay substrate; and
the first power line is in the same layer as the source and drain metal layer.

9 . The display substrate according to claim 1 , wherein the display region comprises a driving structure layer arranged on the underlay substrate, and the driving structure layer comprises a semiconductor layer, a first gate metal layer, a second gate metal layer, and a source and drain metal layer which are arranged on the underlay substrate; and
the first power line, the second connection line and the source and drain metal layer are in the same layer.

10 . The display substrate according to claim 1 , wherein the pixel driving circuit comprises a first transistor to a fourth transistor;
a control electrode of the first transistor is connected with a second scanning signal line, a first electrode of the first transistor is connected with a second initial signal line, and a second electrode of the first transistor is connected with a first node; a first electrode of the second transistor is connected with the first node, and a second electrode of the second transistor is connected with a third node; a control electrode of the third transistor is connected with the first node, a first electrode of the third transistor is connected with a second node, and a second electrode of the third transistor is connected with the third node; a control electrode of the fourth transistor is connected with a first scanning signal line, a first electrode of the fourth transistor is connected with a data signal line, and a second electrode of the fourth transistor is connected with the second node; and the anode of the light emitting element is connected with a fourth node, and the cathode of the light emitting element is connected with the first power line.

11 . The display substrate according to claim 10 , wherein the pixel driving circuit further comprises a fifth transistor and a sixth transistor;
a control electrode of the fifth transistor is connected with a light emitting signal line, a first electrode of the fifth transistor is connected with a second power line, and a second electrode of the fifth transistor is connected with the second node; a control electrode of the sixth transistor is connected with the light emitting signal line, a first electrode of the sixth transistor is connected with the third node, and a second electrode of the sixth transistor is connected with the fourth node.

12 . A display device, comprising the display substrate according to claim 1 .

13 . A display substrate, comprising:
a display region and a peripheral region on a periphery of the display region, wherein at least multiple sub-pixels are arranged in the display region, and at least one of the at least multiple sub-pixels comprises a pixel driving circuit arranged on an underlay substrate and a light emitting element connected with the pixel driving circuit; the light emitting element comprises an anode, a light emitting layer and a cathode, and the cathode is electrically connected with a first power line; and the first power line and a signal connection line are arranged in the peripheral region, and a first initial signal line is connected with the first power line through the signal connection line in the peripheral region; wherein the first initial signal line is arranged in the display region and along a column direction of the at least multiple sub-pixels; and the signal connection line comprises a third connection line, and the third connection line and the first power line are integrated.

14 . A display device, comprising the display substrate according to claim 13 .

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Du Lili
• Wang Benlian
• Long Yue
• Huang Weiyun
• Wang Binyan

Classifications

• H10K59/8731

  multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/353

  characterised by the geometrical arrangement of the RGB subpixels · CPC title