Display substrate, preparing method therefor, and display device

US12520668B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12520668-B2
Application numberUS-202218018563-A
CountryUS
Kind codeB2
Filing dateFeb 23, 2022
Priority dateFeb 23, 2022
Publication dateJan 6, 2026
Grant dateJan 6, 2026

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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A display substrate, a preparation method therefor, and a display device. A display substrate includes a plurality of conductive layers disposed on a silicon-based substrate (101), a conductive layer includes a first sub-electrode plate (110) and a second sub-electrode plate (120), the first sub-electrode plate (110) and the second sub-electrode plate (120) form a first storage capacitor of a MOM capacitance structure, and another conductive layer comprises a third sub-electrode plate (130) and a fourth sub-electrode plate (140), the third sub-electrode plate (130) and the fourth sub-electrode plate (140) form a second storage capacitor of a MOM capacitance structure; the first sub-electrode plate (110) and the fourth sub-electrode plate (140) constitute a third storage capacitor of a MIM capacitance structure, and/or the second sub-electrode plate (120) and the third sub-electrode plate (130) constitute a fourth storage capacitor of a MIM capacitance structure.

First claim

Opening claim text (preview).

The invention claimed is: 1 . A display substrate, comprising a plurality of sub-pixels, wherein at least one sub-pixel comprises a pixel driving circuit, the pixel driving circuit comprises a plurality of transistors and a storage capacitor; on a plane perpendicular to the display substrate, the display substrate comprises a plurality of conductive layers disposed on a silicon-based substrate, one of the plurality of the conductive layers comprises a comb-shaped first sub-electrode plate and a comb-shaped second sub-electrode plate, the first sub-electrode plate and the second sub-electrode plate constitute a first storage capacitor of a metal-oxide-metal capacitor structure, and another conductive layer of the plurality of the conductive layers comprises a comb-shaped third sub-electrode plate and a comb-shaped fourth sub-electrode plate, the third sub-electrode plate and the fourth sub-electrode plate constitute a second storage capacitor of a metal-oxide-metal capacitor structure; an orthographic projection of the first sub-electrode plate on the silicon-based substrate is at least partially overlapped with an orthographic projection of the fourth sub-electrode plate on the silicon-based substrate to form a third storage capacitor of a metal-insulator-metal capacitor structure, and/or an orthographic projection of the second sub-electrode plate on the silicon-based substrate is at least partially overlapped with an orthographic projection of the third sub-electrode plate on the silicon-based substrate to form a fourth storage capacitor of a metal-insulator-metal capacitor structure. 2 . The display substrate according to claim 1 , wherein the first sub-electrode plate is connected to the third sub-electrode plate and the second sub-electrode plate is connected to the fourth sub-electrode plate. 3 . The display substrate according to claim 1 , wherein the first sub-electrode plate comprises a first base part and a plurality of first electrode parts, and the second sub-electrode plate comprises a second base part and a plurality of second electrode parts; the first base part and the second base part are both strip-shaped extending along a second direction and are disposed opposite to each other in a first direction, and the first direction intersects with the second direction; the plurality of the first electrode parts and the plurality of the second electrode parts are alternately disposed in the second direction, first ends of the first electrode parts are connected to the first base part, second ends of the first electrode parts extend toward a direction of the second base part, and at least one first electrode part is located between two adjacent second electrode parts in the second direction; first ends of the second electrode parts are connected to the second base part, second ends of the second electrode parts extend toward a direction of the first base part, and at least one second electrode part is located between two adjacent first electrode parts in the second direction. 4 . The display substrate according to claim 1 , wherein the third sub-electrode plate comprises a third base part and a plurality of third electrode parts, and the fourth sub-electrode plate comprises a fourth base part and a plurality of fourth electrode parts; the third base part and the fourth base part are both strip-shaped extending along a second direction and are disposed opposite to each other in a first direction, the first direction intersects with the second direction; the plurality of the third electrode parts and the plurality of the fourth electrode parts are alternately disposed in the second direction, first ends of the third electrode parts are connected to the third base part, second ends of the third electrode parts extend toward a direction of the fourth base part, and at least one third electrode part is located between two adjacent fourth electrode parts in the second direction; first ends of the fourth electrode parts are connected to the fourth base part, second ends of the fourth electrode parts extend toward a direction of the third base part, and at least one fourth electrode part is located between two adjacent third electrode parts in the second direction. 5 . The display substrate according to claim 1 , wherein an orthographic projection of a first base part of the first sub-electrode plate on the silicon-based substrate is at least partially overlapped with an orthographic projection of a third base part of the third sub-electrode plate on the silicon-based substrate, and the third base part is connected to the first base part through a via, wherein an orthographic projection of a first electrode part of the first sub-electrode plate on the silicon-based substrate is at least partially overlapped with an orthographic projection of a fourth electrode part of the fourth sub-electrode plate on the silicon-based substrate. 6 . The display substrate according to claim 1 , wherein an orthographic projection of a second base part of the second sub-electrode plate on the silicon substrate is at least partially overlapped with an orthographic projection of a fourth base part of the fourth sub-electrode plate on the silicon-based substrate, and the fourth base part is connected to the second base part through a via, wherein an orthographic projection of a second electrode part of the second sub-electrode plate on the silicon-based substrate is at least partially overlapped with an orthographic projection of a third electrode part of the third sub-electrode plate on the silicon-based substrate. 7 . The display substrate according to claim 1 , wherein among the plurality of the conductive layers, a conductive layer comprises a plate-shaped lower electrode plate, another conductive layer on a side of the lower electrode plate away from the silicon-based substrate comprises a plate-shaped upper electrode plate, an orthographic projection of the upper electrode plate on the silicon-based substrate is at least partially overlapped with an orthographic projection of the lower electrode plate on the silicon-based substrate, the lower electrode plate and the upper electrode plate constitute a fifth storage capacitor of a metal-insulator-metal capacitor structure, the upper electrode plate is connected to the first sub-electrode plate and the third sub-electrode plate, and the lower electrode plate is connected to the second sub-electrode plate and the fourth sub-electrode plate. 8 . The display substrate according to claim 7 , wherein the lower electrode plate comprises a first plate body and a second plate body connected to each other, the second plate body being disposed on a side of the first plate body in a second direction, or the second plate body being disposed on a side of the first plate body in a direction opposite to the second direction; an edge on a side of the first plate body in the first direction is flush with an edge on a side of the second plate body in the first direction, or an edge on a side of the first plate body in a direction opposite to the first direction is flush with an edge on a side of the second plate body in a direction opposite to the first direction, and the first direction intersects with the second direction. 9 . The display substrate according to claim 8 , wherein in two adjacent sub-pixels in the first direction, a second plate body in one sub-pixel is provided on a side of the first plate body in the second direction, and a second plate body in the other sub-pixel is provided on a side of the first plate body in a direction opposite to the second direction. 10 . The display substrate according to claim 8 , wherein in two adjacent sub-pixels in the first direction, edges of the first plate bo

Assignees

Inventors

Classifications

  • Manufacture or treatment · CPC title

  • Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

  • the pixel elements being capacitors · CPC title

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What does patent US12520668B2 cover?
A display substrate, a preparation method therefor, and a display device. A display substrate includes a plurality of conductive layers disposed on a silicon-based substrate (101), a conductive layer includes a first sub-electrode plate (110) and a second sub-electrode plate (120), the first sub-electrode plate (110) and the second sub-electrode plate (120) form a first storage capacitor of a M…
Who is the assignee on this patent?
Beijing Boe Display Tech Co, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/1216. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 06 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).