Concept for segmenting an application buffer into data packets

Patent metadata

Field	Value
Publication number	US-12519741-B2
Application number	US-202418665632-A
Country	US
Kind code	B2
Filing date	May 16, 2024
Priority date	May 18, 2018
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

An apparatus, a method, and a computer program for generating data packets according to a transport protocol from an application buffer comprising a plurality of data streams is provided. The apparatus comprises an input circuit configured to receive metadata comprising at least one of information about data packet types supported by the transport protocol, information about an offset and a length of the supported data packet types, and information about possible stream header start positions, possible payload start positions and possible offsets in the data streams. Further, the apparatus comprises a parsing circuit configured to identify offsets in an application buffer as possible segmentation points based on the metadata, to segment the application buffer at the possible segmentation points into segments for data packets, and to generate data packets according to the transport protocol based on the segments. Furthermore, an apparatus, a method and a computer program for processing the application buffer is provided.

First claim

What is claimed is:

1 . Apparatus for use in association with a network, the apparatus comprising:
hardware offload circuitry for use in implementing, at least in part, hardware offload of Quick User Datagram Protocol Internet Connections (QUIC) protocol processing, the QUIC protocol processing to be associated, at least in part, with packet data transmission and/or packet data reception via the network, the QUIC protocol processing to be implemented, at least in part, via the hardware offload comprising one or more of:
QUIC transport-related processing;
QUIC stream-related processing; and/or
QUIC segmentation-related processing;
wherein:
the hardware offload of the QUIC protocol processing is to be based, at least in part, upon information concerning supported packet protocol type and maximum segment size of the supported packet protocol type.

2 . The apparatus of claim 1 , wherein:
the QUIC protocol processing is associated, at least in part, with connection ID data processing.

3 . The apparatus of claim 1 , wherein:
the QUIC protocol processing is associated, at least in part, with congestion information.

4 . The apparatus of claim 1 , wherein:
the QUIC protocol processing is associated, at least in part, with header data processing.

5 . The apparatus of claim 1 , wherein:
the hardware offload comprises use of metadata.

6 . A method to be implemented in association with hardware offload circuitry and a network, the method comprising:
using the hardware offload circuitry in implementing, at least in part, hardware offload of Quick User Datagram Protocol Internet Connections (QUIC) protocol processing, the QUIC protocol processing to be associated, at least in part, with packet data transmission and/or packet data reception via the network, the QUIC protocol processing to be implemented, at least in part, via the hardware offload comprising one or more of:
QUIC transport-related processing;
QUIC stream-related processing; and/or
QUIC segmentation-related processing;
wherein:
the hardware offload of the QUIC protocol processing is to be based, at least in part, upon information concerning supported packet protocol type and maximum segment size of the supported packet protocol type.

7 . The method of claim 6 , wherein:
the QUIC protocol processing is associated, at least in part, with connection ID data processing.

8 . The method of claim 6 , wherein:
the QUIC protocol processing is associated, at least in part, with congestion information.

9 . The method of claim 6 , wherein:
the QUIC protocol processing is associated, at least in part, with header data processing.

10 . The method of claim 6 , wherein:
the hardware offload comprises use of metadata.

11 . At least one non-transitory machine-readable storage medium storing instructions to be executed by at least one machine, the at least one machine to be associated with hardware offload circuitry and a network, the instructions when executed by the at least one machine resulting in performance of operations comprising:
configuring the hardware offload circuitry for use in implementing, at least in part, hardware offload of Quick User Datagram Protocol Internet Connections (QUIC) protocol processing, the QUIC protocol processing to be associated, at least in part, with packet data transmission and/or packet data reception via the network, the QUIC protocol processing to be implemented, at least in part, via the hardware offload comprising one or more of:
QUIC transport-related processing;
QUIC stream-related processing; and/or
QUIC segmentation-related processing;
wherein:
the hardware offload of the QUIC protocol processing is to be based, at least in part, upon information concerning supported packet protocol type and maximum segment size of the supported packet protocol type.

12 . The at least one non-transitory machine-readable storage medium of claim 11 , wherein:
the QUIC protocol processing is associated, at least in part, with connection ID data processing.

13 . The at least one non-transitory machine-readable storage medium of claim 11 , wherein:
the QUIC protocol processing is associated, at least in part, with congestion information.

14 . The at least one non-transitory machine-readable storage medium of claim 11 , wherein:
the QUIC protocol processing is associated, at least in part, with header data processing.

15 . The at least one non-transitory machine-readable storage medium of claim 11 , wherein:
the hardware offload comprises use of metadata.

Assignees

• Intel Corp

Inventors

• Louzoun Eliel
• Deval Manasi
• Doyle Stephen
• Elati Noam
• Fleming Patrick
• Bowers Gregory

Classifications

• H04L47/365

  Dynamic adaptation of the packet size · CPC title

• H04L45/74

  Address processing for routing · CPC title

• H04L49/90

  Buffering arrangements · CPC title

• H04L49/9042 Primary

  Separate storage for different parts of the packet, e.g. header and payload · CPC title