Packet offloading method, mobile terminal, and storage medium
US-2021360650-A1 · Nov 18, 2021 · US
Electronic device and communication control method thereof
US12519734B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12519734-B2 |
| Application number | US-202418757022-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 27, 2024 |
| Priority date | Dec 31, 2021 |
| Publication date | Jan 6, 2026 |
| Grant date | Jan 6, 2026 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
Electronic devices according to present disclosure may comprise: a communication circuit which supports a plurality of communication links including a first link and a second link through a plurality of frequency bands; and at least one processor, wherein the at least one processor is configured to: distribute data packets to be transmitted at least one of the plurality of communication links, respectively; identify a first transmission rate of the first link and a second transmission rate of the second link; and perform at least one of an adjustment of the transmission rates or an adjustment of the number of distribution of data packets for the first link and the second link so that a difference between transmission times of the data packets distributed to the first link and the second link, respectively, is within a designated time range.
First claim
Opening claim text (preview).
The invention claimed is: 1 . An electronic device comprising: a memory; a communication circuit configured to support multiple communication links including a first link and a second link; and a processor operatively connected to the communication circuit and the memory, wherein the memory stores instructions that, when executed by the processor individually or collectively, cause the electronic device to: distribute data packets to be transmitted through the communication circuit to at least two of the multiple communication links, including the first link and the second link; identify a first transmission rate of the first link and a second transmission rate of the second link; and perform at least one of an adjustment of the first transmission rate or the second transmission rate or an adjustment of a first number of data packets distributed to the first link or a second number of data packets distributed to the second link so that a difference between a first transmission time of data packets distributed to the first link and a second transmission time of data packets distributed to the second link is within a designated time range, based on the first transmission rate, the second transmission rate, and a total number of data packets transmitted through the multiple communication links. 2 . The electronic device of claim 1 , wherein the memory stores instructions that, when executed by the processor individually or collectively, cause the electronic device to, in a case that the first number of data packets distributed to the first link and the second number of data packets distributed to the second link are designated respectively, redistribute at least one of the packets distributed to the second link to the first link, wherein the second transmission time is longer than the first transmission time. 3 . The electronic device of claim 2 , wherein the memory stores instructions that, when executed by the processor individually or collectively, cause the electronic device to, by using the first transmission rate and the first number of data packets, and the second transmission rate and the second number of data packets, calculate a number of data packets to be redistributed from the second link to the first link based on an inverse ratio between the first transmission rate and the second transmission rate. 4 . The electronic device of claim 1 , wherein the memory stores instructions that, when executed by the processor individually or collectively, cause the electronic device to identify the total number of data packets transmitted through the multiple communication links, the first transmission rate of the first link, and the second transmission rate of the second link, and calculate the first number of data packets to be distributed to the first link and the second number of data packets to be distributed to the second link. 5 . The electronic device of claim 4 , wherein the memory stores instructions that, when executed by the processor individually or collectively, cause the electronic device to calculate the first number of data packets to be distributed to the first link and calculate the second number of data packets to be distributed to the second link, based on a ratio between the first transmission rate and the second transmission rate. 6 . The electronic device of claim 1 , wherein the memory stores instructions that, when executed by the processor individually or collectively, cause the electronic device to, in a case that the first number of data packets distributed to the first link and the second number of data packets distributed to the second link are designated respectively, calculate the first transmission time of the first link according to the first transmission rate and the second transmission time of the second link according to the second transmission rate, and adjust at least one of the first transmission rate or the second transmission rate based on a difference between the first transmission time and the second transmission time. 7 . The electronic device of claim 6 , wherein the memory stores instructions that, when executed by the processor individually or collectively, cause the electronic device to adjust the first transmission rate or the second transmission rate by lowering the first transmission rate by one level in an associated modulation and coding scheme (MCS) table, or increasing the second transmission rate by one level in the associated MCS table, wherein the first transmission rate is faster than the second transmission rate. 8 . The electronic device of claim 7 , wherein the memory stores instructions that, when executed by the processor individually or collectively, cause the electronic device to, in a case of increasing the second transmission rate of the second link by one level in the associated modulation and coding scheme (MCS) table, estimate a signal to noise ratio (SNR) according to a previous transmission rate, calculate a bit error ratio (BER) of the second link based on the estimated SNR, and increase the second transmission rate of the second link by one level in the associated MCS table, when the calculated BER is less than a designated value. 9 . The electronic device of claim 7 , wherein the memory stores instructions that, when executed by the processor individually or collectively, cause the electronic device to calculate a data packet transmission time of the first link and the second link, in a case of lowering the first transmission rate of the first link by one level in the associated modulation and coding scheme (MCS) table, and to lower the transmission rate of the first link by one level in the associated MCS table, in a case that the transmission time of the first link is faster than the transmission time of the second link. 10 . The electronic device of claim 1 , wherein the multiple communication links comprise multiple communication links among a communication link of a 2.4 GHz frequency band, a communication link of a 5 GHz frequency band, or a communication link of a 6 GHz frequency band. 11 . A method performed by an electronic device, the method comprising: distributing data packets to be transmitted through multiple communication links including a first link and a second link to at least two of the multiple communication links, including the first link and the second link; identifying a first transmission rate of the first link and a second transmission rate of the second link; and performing at least one of an adjustment of the first transmission rate or the second transmission rate or an adjustment of a first number of data packets distributed to the first link or a second number of data packets distributed to the second link so that a difference between a first transmission time of data packets distributed to the first link and a second transmission time of data packets distributed to the second link is within a designated time range, based on the first transmission rate, the second transmission rate, and a total number of data packets transmitted through the multiple communication links. 12 . The method of claim 11 , further comprising, in a case that the first number of data packets distributed to the first link and the second number of data packets distributed to the second link are designated respectively, redistributing at least one of the packets distributed to the second link to the first link, wherein the second transmission time is longer than the first transmission time. 13 . The method of claim 12 , further comprising, by using the first transmission rate and the first number of data packets, and the second transmission rate and the second number o
Assignees
Inventors
Classifications
Transcoding devices; Rate adaptation devices · CPC title
Setup of multiple wireless link connections · CPC title
Multichannel or multilink protocols · CPC title
Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title
Service support devices; Network management devices · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US12519734B2 cover?
- Electronic devices according to present disclosure may comprise: a communication circuit which supports a plurality of communication links including a first link and a second link through a plurality of frequency bands; and at least one processor, wherein the at least one processor is configured to: distribute data packets to be transmitted at least one of the plurality of communication links, …
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H04L47/25. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jan 06 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).