Semiconductor device

Patent metadata

Field	Value
Publication number	US-12519487-B2
Application number	US-202418590903-A
Country	US
Kind code	B2
Filing date	Feb 28, 2024
Priority date	Mar 9, 2023
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A semiconductor device includes an input port, a pulse generation circuit, and a serial-parallel conversion circuit. The input port is connected to an input port of the pulse generation circuit and a data signal input port of the serial-parallel conversion circuit. A signal received at the input port is a start bit and a data signal. The pulse generation circuit includes a delay circuit. A clock signal output port of the pulse generation circuit is connected to a clock signal input port of the serial-parallel conversion circuit.

First claim

What is claimed is:

1 . A semiconductor device comprising:
an input port; a pulse generation circuit; and a serial-parallel conversion circuit, a gate circuit control signal generation circuit, wherein the input port is connected to a data signal input port of the serial-parallel conversion circuit and an input port of the pulse generation circuit, a signal received at the input port is a start bit and a data signal, the pulse generation circuit comprises a delay circuit, and an output port of the pulse generation circuit is connected to a clock signal input port of the serial-parallel conversion circuit, and the output port of the pulse generation circuit is further connected to an input port of the gate circuit control signal generation circuit, wherein the gate circuit control signal generation circuit comprises a binary counter and a combination circuit which constitutes a decoder, an output port of the binary counter is connected to an input port of the combination circuit which constitutes the decoder, and the combination circuit which constitutes the decoder is composed of a logical configuration capable of outputting active logic at a desired count value.

2 . The semiconductor device according to claim 1 , further comprising:
a gate circuit; and a fuse circuit, wherein the gate circuit is connected between the serial-parallel conversion circuit and the fuse circuit.

3 . The semiconductor device according to claim 2 , wherein the data signal is a 1-bit data signal.

4 . The semiconductor device according to claim 2 , wherein the pulse generation circuit is a one-shot pulse generation circuit.

5 . The semiconductor device according to claim 1 , wherein the data signal is a 1-bit data signal.

6 . The semiconductor device according to claim 1 , wherein the pulse generation circuit is a one-shot pulse generation circuit.

7 . The semiconductor device according to claim 1 , wherein the binary counter is a ripple counter.

8 . The semiconductor device according to claim 1 , wherein the pulse generation circuit is configured to, in response to a change of the start bit from a low level to a high level at the input port of the semiconductor device, generate and output multiple positive polarity pulses on a clock output signal.

9 . The semiconductor device according to claim 8 , wherein
the clock signal input port of the serial-parallel conversion circuit is configured to receive the clock signal output from the pulse generation circuit, and upon an entrance of the signal combining the start bit and data bits to the input port, the serial-parallel conversion circuit is configured to capture values of the data bits in the signal received at the input port at a rising edge of the multiple positive polarity pulses on the clock signal to generate output signals of the serial-parallel conversion circuit.

10 . The semiconductor device according to claim 9 , wherein
a shift operation is performed to shift a value in one of the output signals of the serial-parallel conversion circuit to another one of the output signals of the serial-parallel conversion circuit.

11 . The semiconductor device according to claim 8 , wherein the pulse generation circuit is a double pulse generation circuit.

Assignees

• Ablic Inc

Inventors

• Kuroda Tadakatsu

Classifications

• H03K3/037

  Bistable circuits · CPC title

• H03K2005/00013

  Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse · CPC title

• H03K5/01 Primary

  Shaping pulses (discrimination against noise or interference H03K5/125) · CPC title

• H03K5/15

  Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors (distributing, switching or gating arrangements H03K17/00) · CPC title

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title