Modular and dynamic digital control in a quantum controller

Patent metadata

Field	Value
Publication number	US-12518189-B2
Application number	US-202318503521-A
Country	US
Kind code	B2
Filing date	Nov 7, 2023
Priority date	May 2, 2019
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

A quantum controller comprises a quantum control pulse generation circuit and digital signal management circuit. The quantum control pulse generation circuit is operable to generate a quantum control pulse which can be processed by any of a plurality of controlled circuits, and generate a first digital signal which can be routed to any of the plurality of controlled circuits. The digital signal management circuit is operable to detect, during runtime, to which one or more of the plurality of controlled circuits the first digital signal is to be routed, to manipulate the first digital signal based on the one or more of the plurality of controlled circuits to which the first digital signal is to be routed, where the manipulation results in one or more manipulated digital signals, and to route the one or more manipulated digital signals to one or more of the plurality of controlled circuits.

First claim

What is claimed is:

1 . A system comprising:
a pulser configured to generate a quantum control pulse and one or more control signals, wherein the pulser is one of a plurality of pulsers each configured to emit a shaped analog pulse responsive to a digital pulse control signal; and a pulse operations manager operable to manipulate the one or more control signals, wherein:
the pulse operations manager comprises circuitry operable to configure pulse operations applied to a particular raw outbound pulse such that the manipulation is tailored to the particular raw outbound pulse, and
the pulse operations manager operable to send the one or more manipulated control signals to one or more controlled circuits.

2 . The system of claim 1 , wherein the manipulation comprises a delay according to a propagation time of the quantum control pulse from the pulser to one of the one or more controlled circuits.

3 . The system of claim 2 , wherein the pulse operations manager is operable to:
delay a first of the one or more control signals intended for a first of the one or more controlled circuits by a first amount of time; and delay a second of the one or more control signals intended for a second of the one or more controlled circuits by a second amount of time.

4 . The system of claim 1 , wherein the manipulation comprises a convolution of by a digital bit pattern.

5 . The system of claim 4 , wherein the pulse operations manager is operable to select the digital bit pattern from a plurality of digital bit patterns according to the one or more controlled circuits.

6 . The system of claim 5 , wherein the pulse operations manager is operable to:
convolve a first control signal of the one or more control signals with a first digital bit pattern of the plurality of digital bit patterns to generate a first manipulated control signal of the one or more manipulated control signals; and convolve the first control signal with a second digital bit pattern of the plurality of digital bit patterns to generate a second manipulated control signal of the one or more manipulated control signals.

7 . The system of claim 1 , wherein:
the one or more controlled circuits comprise a gating circuit, wherein:
when the gating circuit is closed, the quantum control pulse is permitted to propagate to a destination;
when the gating circuit is open, the quantum control pulse is prevented from propagating to the destination; and
at least one of the one or more manipulated control signals controls whether the gating circuit is closed or open.

8 . The system of claim 7 , wherein the destination is a quantum processor.

9 . The system of claim 7 , wherein:
the gating circuit is part of an input manager circuit configured to receive a return of the quantum control pulse from a quantum processor; and the destination is a quantum control pulse generation circuit.

10 . The system of claim 1 , wherein a first control signal of the one or more control signals is routed according to a second control signal of the one or more control signals.

11 . The system of claim 10 , wherein:
the second control signal is a multi-bit signal; a state of each bit of the second control signal determines whether the first digital signal is to be routed to a respective one of the one or more controlled circuits.

12 . The system of claim 1 , wherein:
the pulse operations manager comprises a plurality of processing paths; and each of the plurality of processing paths is configured to manipulate the one or more control signals.

13 . The system of claim 12 , wherein:
a first processing path of the plurality of processing paths is configured to introduce a first delay to the one or more control signals; a second processing path of the plurality of processing paths is configured to introduce a second delay to the one or more control signals; and the first delay is different than the second delay.

14 . The system of claim 12 , wherein:
a first processing path of the plurality of processing paths is configured to convolve the one or more control signals with a first bit pattern; a second processing path of the plurality of processing paths is configured to convolve the one or more control signals with a second bit pattern; and the first bit pattern is different than the second bit pattern.

15 . The system of claim 12 , wherein:
the pulse operations manager is operable to select which of the plurality of processing paths to route a first control signal of the one or more control signals according to a second control signal of the one or more control signals.

16 . The system of claim 15 , wherein:
the second control signal comprises a first bit and a second bit; a state of the first bit of the second control signal determines whether the first control signal is to be processed by the first processing path; and a state of the second bit of the second control signal determines whether the first control signal is to be processed by the second processing path.

17 . The system of claim 1 , wherein:
the one or more controlled circuits comprise a switch; and one of the one or more manipulated control signals controls the switch.

18 . The system of claim 1 , wherein:
the one or more controlled circuits comprise a measurement device; and one of the one or more manipulated control signals triggers the measurement device.

19 . The system of claim 1 , wherein:
the one or more controlled circuits comprise a control device; and one of the one or more manipulated control signals triggers the operation of the control device.

20 . The system of claim 1 , wherein:
the one or more controlled circuits comprise an amplifier; and one of the one or more manipulated control signals controls a gain of the amplifier.

Assignees

• Quantum Machines
• Q M Tech Ltd

Inventors

• Cohen Yonatan
• Ofek Nissim
• Sivan Itamar

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• G06N10/40 Primary

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title