Method and architecture for fuzzy-logic using unary processing

US12518186B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12518186-B2
Application numberUS-202117340834-A
CountryUS
Kind codeB2
Filing dateJun 7, 2021
Priority dateJun 8, 2020
Publication dateJan 6, 2026
Grant dateJan 6, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

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Efficient hardware design of the fuzzy-inference engine has become necessary for high-performance applications. The disclosed technology applies unary processing to the platform of fuzzy-logic. To mitigate the latency, the proposed design processes right-aligned bit-streams. A one-hot decoder is used for fast detection of the bit-stream with maximum value. Implementing a fuzzy-inference engine with 81 fuzzy-inference rules, the disclosed architecture provides 82%, 46%, and 67% saving in the hardware area, power and energy consumption, respectively, and 94% reduction in the number of used LUTs compared to conventional binary implementation.

First claim

Opening claim text (preview).

We claim: 1 . An architecture for performing fuzzy interference in unary computing systems, comprising: a fuzzification module; a unary number generator; a rule-apply module; an aggregation module; and a defuzzification module, comprising: one or more inputs comprising aggregated values; a database comprising at least one prestored value; a one-hot decoder; and a MUX unit; wherein the aggregated values comprise one or more outputs from the aggregation module; wherein the aggregated values further comprise corresponding unary bit-streams; and wherein the one-hot decoder comprises functionality to detect which unary bit-stream has the maximum value. 2 . The architecture of claim 1 , wherein the unary number generator comprises: a down counter; and two or more comparators. 3 . The architecture of claim 1 , wherein the unary number generator consists of: one down counter; and two or more comparators. 4 . A method for performing fuzzy interference in unary computing systems, comprising: a. providing an architecture, comprising: a fuzzification module; a unary number generator a rule-apply module; an aggregation module; and a defuzzification module; b. performing a fuzzification process by the fuzzification module, comprising converting one or more crisp inputs to one or more fuzzy linguistic values; c. converting numbers in a range of [0,1] of the fuzzy linguistic values to unary bit-streams by the unary number generator; d. applying one or more inference rules by the rule-apply module; e. aggregating one or more outputs of the rule-apply module; and f. performing a defuzzification process by the defuzzification module, wherein the fuzzy linguistic values are converted to one or more crisp value outputs. 5 . The method of claim 4 , wherein the unary number generator comprises: a down counter; and two or more comparators. 6 . The method of claim 4 , wherein the crisp input conversion is based on an input membership function. 7 . The method of claim 4 , wherein the unary number generator consists of: one down counter; and two or more comparators. 8 . The method of claim 4 , wherein the defuzzification module comprises: one or more inputs comprising aggregated values; a database comprising at least one prestored value; a one-hot decoder; and a MUX unit; wherein the aggregated values comprise one or more outputs from the aggregation module; and wherein the aggregated values further comprise corresponding unary bit-streams. 9 . The method of claim 8 , further comprising: transmitting the unary bit-streams corresponding the aggregated values to the one-hot decoder; detecting the unary bit-stream with the maximum value by the one-hot decoder; upon the one-hot decoder detecting the maximum value unary bit-stream, a corresponding index of the maximum value unary bit-stream is sent to the MUX unit; and the MUX unit selects a corresponding defuzzification value. 10 . The method of claim 8 , wherein the unary bit-stream with the maximum value comprises the bit-stream that generates a 1 in the respective bit-stream first before the other unary bit-streams.

Assignees

Inventors

Classifications

  • Unary operations; Data partitioning operations · CPC title

  • Development tools for entering the parameters of a fuzzy system · CPC title

  • G06N7/023Primary

    Learning or tuning the parameters of a fuzzy system · CPC title

  • G06N5/048Primary

    Fuzzy inferencing · CPC title

  • Physical realisation · CPC title

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What does patent US12518186B2 cover?
Efficient hardware design of the fuzzy-inference engine has become necessary for high-performance applications. The disclosed technology applies unary processing to the platform of fuzzy-logic. To mitigate the latency, the proposed design processes right-aligned bit-streams. A one-hot decoder is used for fast detection of the bit-stream with maximum value. Implementing a fuzzy-inference engine …
Who is the assignee on this patent?
Univ Louisiana At Lafayette
What technology area does this patent fall under?
Primary CPC classification G06N7/023. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 06 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).