Electronic devices, including memory devices, and operating methods thereof

Patent metadata

Field	Value
Publication number	US-12517833-B2
Application number	US-202418762201-A
Country	US
Kind code	B2
Filing date	Jul 2, 2024
Priority date	Aug 31, 2023
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

The present disclosure relates to an electronic device, a memory device, and an operating method of the memory device. An example memory device includes a first bank, a second bank, and a cache controller. The cache controller is configured to set a hash function based on a power control signal that comprises instructions to stop supplying power to the first bank, and to map the first address and the second bank based on the hash function and a first transaction provided by a master after the power control signal is input.

First claim

What is claimed is:

1 . A memory device comprising:
a first bank configured to
receive power, and
store at least one cacheline corresponding to a first address group;
a second bank configured to
receive the power, and
store at least one cacheline corresponding to a second address group; and
a cache controller configured to
set a hash function based on a power control signal that comprises instructions to suspend supply of the power to the first bank, and
based on the hash function, a first address provided by a master after the power control signal is input, and a first transaction including a first target indicating the first bank, map the first address and the second bank.

2 . The memory device of claim 1 , wherein the cache controller comprises:
a first hash function configured to
output the first target based on the first address group, and
output a second target indicating the second bank based on the second address group; and
a second hash function configured to output the second target based on the first address group and the second address group, wherein the cache controller is configured to change, based on the power control signal, from the first hash function to the second hash function.

3 . The memory device of claim 1 , wherein the cache controller is configured to
determine whether the first transaction is a cache hit with respect to the at least one cacheline stored in the first bank, and respond to the first transaction according to a result of the cache hit.

4 . The memory device of claim 3 , wherein the cache controller is configured to
based on the cache hit occurring, provide, to the master, a cacheline corresponding to the first transaction, provide, to the master, a second target indicating the second bank, a storage request instructing to store the cacheline, and a first internal transaction comprising the first address, or forward, to the second bank, the second target, the storage request, and the first internal transaction, and control the first bank to invalidate the cacheline stored in the first bank.

5 . The memory device of claim 1 , wherein the cache controller is configured to
based on a cache miss occurring, change the first target to a second target, the second target indicating the second bank, and provide, to the master, a second internal transaction, the second internal transaction comprising the second target and the first address, or forward the second internal transaction to the second bank.

6 . The memory device of claim 1 , wherein the cache controller is configured to
control the first bank to perform a flush operation that flushes the at least one cacheline stored in the first bank, and based on the flush operation on the first bank being performed, receive the first transaction.

7 . The memory device of claim 6 , wherein the cache controller is configured to
based on the flush operation being completed, provide, to the master, a response signal notifying to change a hash function comprised in the master.

8 . The memory device of claim 1 , wherein the cache controller is comprised in the first bank.

9 . A memory device comprising:
a first bank configured to receive power based on a power control signal that comprises instructions to supply the power; a second bank configured to
store at least one first cacheline corresponding to a first address group, the first address group being provided before the first bank receives the power, and
store at least one second cacheline corresponding to a second address group; and
a cache controller configured to
set a hash function based on the power control signal, and
based on the hash function, a first address provided by a master after the power control signal is input, and a first transaction including a second target indicating the second bank, map the first address to the first bank.

10 . The memory device of claim 9 , wherein the cache controller comprises:
a first hash function configured to
output a first target indicating the first bank based on the first address group, and
output the second target based on the second address group; and
a second hash function configured to output the second target based on the first address group and the second address group, wherein the cache controller is configured to change, based on the power control signal, from the second hash function to the first hash function.

11 . The memory device of claim 9 , wherein the cache controller is configured to
determine whether the first transaction is a cache hit with respect to the at least one first cacheline, and respond to the first transaction according to a result of the cache hit.

12 . The memory device of claim 11 , wherein the cache controller is configured to
based on the cache hit occurring, provide, to the master, a first cacheline corresponding to the first transaction, provide, to the master, a first target indicating the first bank, a storage request instructing to store the first cacheline, and a first internal transaction comprising the first address, or forward, to the first bank, the first target, the storage request, and the first internal transaction, and control the first bank to invalidate the first cacheline stored in the second bank.

13 . The memory device of claim 11 , wherein the cache controller is configured to
based on a cache miss occurring, change the second target to a first target, the first target indicating the first bank, and provide, to the master, a second internal transaction, the second internal transaction comprising the first target and the first address, or forward the second internal transaction to the first bank.

14 . The memory device of claim 9 , wherein the cache controller is configured to
control the second bank to perform a flush operation that flushes the at least one first cacheline stored in the second bank, and based on the flush operation on the second bank being performed, receive the first transaction.

15 . The memory device of claim 14 , wherein the cache controller is configured to
based on the flush operation being completed, provide, to the master, a response signal notifying to change a hash function comprised in the master.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Moongyung
• Eom Youngsik
• Ham Donghyeon

Classifications

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F1/3225

  of memory devices · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title