Optimized XOR loading to SRAM and HMB

Patent metadata

Field	Value
Publication number	US-12517677-B2
Application number	US-202418584081-A
Country	US
Kind code	B2
Filing date	Feb 22, 2024
Priority date	Feb 22, 2024
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

Selectively writing relevant bins directly to a controller's volatile memory (e.g., SRAM) based on a next-to-write address and writing the remaining bins to a host's volatile memory (e.g., DRAM or HMB), avoids the need for any additional reads from host's volatile memory and writes from controller's volatile memory. Avoiding the need for any additional reads from host's volatile memory, which has a slower access time than controller's volatile memory, improves exit latency from the boot and low-power-state exit flows. Prior to writing the parity bins to the controller or the host, the controller may store parity bins and/or the next-to-write address in non-volatile memory. The next-to-write address is then evaluated to determine whether a party bin is written to the controller's volatile memory or the host's volatile memory.

First claim

What is claimed is:

1 . A data storage device, comprising:
a memory device; and a controller coupled to the memory device, wherein the controller is configured to:
store a plurality of parity bins in non-volatile memory;
determine a next address of a first volatile memory where data should be written;
select at least one parity bin from the plurality of parity bins to write to the first volatile memory, wherein the selecting is based on whether the at least one parity bin is relevant, wherein a parity bin is relevant if the parity bin is associated with the next address of the first volatile memory where data should be written;
write at least one relevant parity bin of the plurality of parity bins to the first volatile memory; and
write non-relevant parity bins of the plurality of parity bins to a second volatile memory.

2 . The data storage device of claim 1 , wherein the non-volatile memory is NAND.

3 . The data storage device of claim 1 , wherein the first volatile memory is static random access memory (SRAM).

4 . The data storage device of claim 1 , wherein the second volatile memory is dynamic random access memory (DRAM) or a host memory buffer (HMB).

5 . The data storage device of claim 1 , wherein the controller is further configured to store the plurality of parity bins to non-volatile memory during a graceful shutdown flow.

6 . The data storage device of claim 1 , wherein writing the at least one relevant parity bin to the first volatile memory occurs during a boot exit flow.

7 . The data storage device of claim 1 , wherein writing the at least one relevant parity bin to the first volatile memory occurs during a low-power-state exit flow.

8 . The data storage device of claim 1 , wherein the controller is further configured to receive acknowledgement from the second volatile memory after writing non-relevant parity bins of the plurality of parity bins to the second volatile memory.

9 . The data storage device of claim 1 , wherein the controller does not receive acknowledgement from the first volatile memory after writing the at least relevant one parity bin to the first volatile memory.

10 . The data storage device of claim 1 , wherein the controller is further configured to:
determine an address of an open block in the first volatile memory, wherein the address of the open block in the first volatile memory is a next address in the first volatile memory where a next data will be written; store the address of the open block in non-volatile memory; write at least one first parity bin to the open block in the first volatile memory; and write at least one second parity bin to the second volatile memory.

11 . The data storage device of claim 1 , wherein the controller is further configured to:
store the plurality of parity bins in non-volatile memory in response to a pre-determined event; determine an address of an open block in the first volatile memory, wherein the address of the open block in the first volatile memory is a next address in the first volatile memory where a next data will be written; store the address of the open block in the first volatile memory; and select at least one parity bin from the plurality of parity bins to write to the first volatile memory during a boot exit flow or a low-power-state exit flow.

12 . The data storage device of claim 1 , wherein each parity bin of the plurality of parity bins is associated with a different address of the first volatile memory.

13 . The data storage device of claim 1 , wherein the first volatile memory has a faster access time than the second volatile memory.

14 . A data storage device, comprising:
a memory device; and a controller coupled to the memory device, wherein the controller is configured to:
determine an address of an open block in a first volatile memory, wherein the address of the open block in the first volatile memory is a next address in the first volatile memory where a next data will be written;
store the address of the open block in non-volatile memory;
select at least one parity bin from a plurality of parity bins to write to the first volatile memory, wherein the selecting is based on whether the at least one parity bin is relevant, wherein a parity bin is relevant if the parity bin is associated with the next address;
write at least one relevant parity bin of the plurality of parity bins to the open block in the first volatile memory; and
write at least one non-relevant parity bin of the plurality of parity bins to a second volatile memory.

15 . The data storage device of claim 14 , wherein the at least one relevant parity bin is triple-level cell (TLC) parity.

16 . The data storage device of claim 14 , wherein the at least one relevant parity bin is single-level cell (SLC) parity.

17 . The data storage device of claim 14 , wherein the controller is further configured to store the plurality of parity bins in non-volatile memory prior to writing the at least one relevant and non-relevant parity bins to volatile memory.

18 . A data storage device, comprising:
means to store data; and a controller coupled to the means to store data, wherein the controller is configured to:
store a plurality of parity bins in non-volatile memory in response to a pre-determined event;
determine an address of an open block in a first volatile memory, wherein the address of the open block in the first volatile memory is a next address in the first volatile memory where a next data will be written;
store the address of the open block in the first volatile memory;
select at least one parity bin from the plurality of parity bins to write to a first volatile memory during a boot exit flow or a low-power-state exit flow, wherein the selecting is based on whether the at least one parity bin is relevant, wherein a parity bin is relevant if the parity bin is associated with the next address of the first volatile memory where data should be written;
write at least one relevant parity bin of the plurality of parity bins to the first volatile memory; and
write non-relevant parity bins of the plurality of parity bins to a second volatile memory.

19 . The data storage device of claim 18 , wherein the pre-determined event is a graceful shutdown of the data storage device.

20 . The data storage device of claim 18 , wherein the controller is further configured to write the at least one parity bin to the open block in the first volatile memory.

Assignees

• Sandisk Technologies Inc

Inventors

• Einav Daphna
• Bublil Lior
• Moshe Eran

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0656 Primary

  Data buffering arrangements · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title