Display panel and display device

Patent metadata

Field	Value
Publication number	US-12517404-B2
Application number	US-202118687586-A
Country	US
Kind code	B2
Filing date	Oct 19, 2021
Priority date	Oct 19, 2021
Publication date	Jan 6, 2026
Grant date	Jan 6, 2026

Abstract

Embodiments of the present disclosure provide a display panel and a display device. The display panel comprises: a base substrate having multiple rows and multiple columns of sub-pixels; and a pixel electrode layer located on the base substrate, the pixel electrode layer comprising a plurality of pixel electrodes arranged apart from each other, and one sub-pixel comprising one pixel electrode, wherein the pixel electrode comprises: a first electrode strip and comb structures respectively connected to both sides of the first electrode strip, each comb structure consisting of a plurality of second electrode strips and a plurality of slits arranged alternately.

First claim

What is claimed is:

1 . A display panel, comprising:
a base substrate, having multiple rows and multiple columns of sub-pixels; a pixel electrode layer, located on the base substrate, wherein the pixel electrode layer comprises a plurality of pixel electrodes arranged at intervals, and one sub-pixel comprises one pixel electrode; data lines between the base substrate and the pixel electrode layer, wherein the data lines comprise a plurality of first-type data lines and a plurality of second-type data lines; the first-type data lines and the second-type data lines are alternately arranged along a row direction; a first insulating layer between the data lines and the pixel electrode layer; a common electrode layer between the first insulating layer and the pixel electrode layer; a plurality of gate lines located between the data lines and the base substrate and insulated and intersected with the data lines; a second insulating layer between the data lines and the gate lines; and common electrode connection lines arranged at intervals on a same layer as the gate lines; wherein, each pixel electrode comprises a first electrode strip, and comb structures respectively connected to both sides of the first electrode strip; the comb structures are composed of a plurality of second electrode strips and a plurality of slits arranged alternately; the gate lines extend along the row direction, and one row of the sub-pixels corresponds to two gate lines; the common electrode connection lines extend along the row direction; and the common electrode connection lines are electrically connected with each of the second-type data lines through via holes penetrating the second insulating layer, and the second-type data lines are connected with the common electrode layer through via holes penetrating the first insulating layer.

2 . The display panel according to claim 1 , wherein a shape of the first electrode strip is a folded line shape.

3 . The display panel according to claim 2 , wherein the first electrode strip is divided into a first sub-electrode strip and a second sub-electrode strip along a bending point; and
the second electrode strips on both sides of the first sub-electrode strip are in one-to-one correspondence and are located on a same straight line, and the second electrode strips on both sides of the second sub-electrode strip are in one-to-one correspondence and are located on a same straight line.

4 . The display panel according to claim 3 , wherein the second electrode strips connected with the first sub-electrode strip are approximately parallel, and the second electrode strips connected with the second sub-electrode strip are approximately parallel.

5 . The display panel according to claim 4 , wherein the second electrode strips connected with the first sub-electrode strip have a first inclination angle to a row direction, the second electrode strips connected with the second sub-electrode strip have a second inclination angle to the row direction, and the first inclination angle and the second inclination angle are supplementary angles.

6 . The display panel according to claim 3 , wherein each pixel electrode has a center line extending along a row direction, and the bending point is substantially located on the center line.

7 . The display panel according to claim 6 , wherein the first electrode strip has a bending angle at a position corresponding to the bending point, and on a side of the bending angle and at a position close to the bending point, the plurality of second electrode strips correspondingly connected with the first sub-electrode strip and the plurality of second electrode strips correspondingly connected with the second sub-electrode strip are electrically connected;
on opposite sides of the bending angle and at two side edges away from the bending point, the plurality of second electrode strips correspondingly connected with the first sub-electrode strip are electrically connected, and the plurality of second electrode strips correspondingly connected with the second sub-electrode strip are electrically connected; and ends, far away from the first electrode strip, of the second electrode strips at other positions are independent from each other.

8 . The display panel according to claim 1 , wherein orthographic projections of the data lines on the base substrate and orthographic projections of effective light-emitting areas of the sub-pixels on the base substrate have an overlapping area, and a shape of the overlapping area is a folded line shape.

9 . The display panel according to claim 8 , wherein an orthographic projection of the first electrode strip on the base substrate substantially overlaps the overlapping area.

10 . The display panel according to claim 9 , wherein the overlapping area forms an isosceles triangle with a column direction;
wherein a bending angle of the overlapping area is larger than 90° and smaller than 180°.

11 . The display panel according to claim 8 , wherein one column of the sub-pixels corresponds to one data line;
each data line comprises a first sub-data line and a second sub-data line electrically connected with each other; an orthographic projection of the first sub-data line on the base substrate and an orthographic projection of an effective light-emitting area of a corresponding sub-pixel on the base substrate form the overlapping area; and an orthographic projection of the second sub-data line on the base substrate does not overlap with an orthographic projection of each effective light-emitting area on the base substrate.

12 . The display panel according to claim 1 , further comprising:
a third insulating layer between the common electrode layer and the pixel electrode layer; wherein the common electrode layer has a planar structure.

13 . The display panel according to claim 8 , wherein, orthographic projections of the common electrode connection lines on the base substrate do not overlap with the orthographic projections of the effective light-emitting areas on the base substrate.

14 . The display panel according to claim 1 , further comprising:
a color resistor layer located between the data lines and the first insulating layer, wherein the color resistor layer comprises a plurality of color resistors arranged corresponding to the sub-pixels.

15 . The display panel according to claim 1 , further comprising: an opposite substrate disposed opposite to the base substrate, and a liquid crystal packaged between the base substrate and the opposite substrate; a color resistor layer is provided on the opposite substrate, and the color resistor layer comprises a plurality of color resistors corresponding to the sub-pixels.

16 . A display device, comprising a display panel, wherein the display panel comprises:
a base substrate, having multiple rows and multiple columns of sub-pixels; a pixel electrode layer, located on the base substrate, wherein the pixel electrode layer comprises a plurality of pixel electrodes arranged at intervals, and one sub-pixel comprises one pixel electrode; data lines between the base substrate and the pixel electrode layer, wherein the data lines comprise a plurality of first-type data lines and a plurality of second-type data lines; the first-type data lines and the second-type data lines are alternately arranged along a row direction; a first insulating layer between the data lines and the pixel electrode layer; a common electrode layer between the first insulating layer and the pixel electrode layer; a plurality of gate lines located between the data line

Assignees

• Fuzhou Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wang Baoqiang
• Xu Xu
• Wang Wenchao
• Xu Shanshan
• Wang Jinliang
• Fang Xin
• Chen Jixiang

Classifications

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G02F1/136222 Primary

  Colour filters incorporated in the active matrix substrate · CPC title

• G02F1/134372

  for fringe field switching [FFS] where the common electrode is not patterned · CPC title

• G02F1/133707

  Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes · CPC title