β-Ga2O3 junction barrier Schottky (JBS) diodes with sputtered p-type NiO

Patent metadata

Field	Value
Publication number	US-12513922-B2
Application number	US-202318340134-A
Country	US
Kind code	B2
Filing date	Jun 23, 2023
Priority date	Jun 24, 2022
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

A self-aligned lithography process for the fabrication of an electronic device having predefined areas of a second semiconductor material having a second conductivity type deposited into trenches formed in a first semiconductor material layer having a first conductivity type. A single lithography mask is used for etching trenches in the first semiconductor material, enabling cleaning of the trenches, and providing defined areas for the deposition of the second semiconductor material into the first semiconductor material. The presence of the areas of the second semiconductor material within the first semiconductor material creates a heterojunction beneath a metal for the formation of a first type of contact to the first semiconductor material and a second type of contact to the second type of material. By using a single mask for the etching, cleaning, and filling steps, misalignment issues plaguing devices having small (1-2 μm) feature sizes is eliminated.

First claim

What is claimed is:

1 . A method for fabricating an electronic device, comprising:
forming a semiconductor material stack including a layer of amorphous or polycrystalline silicon (a-Si/poly-Si) deposited on an upper surface of a first semiconductor material layer, the first semiconductor material having a first type of conductivity; depositing a layer of SiO 2 on an upper surface of the a-Si/poly-Si layer; depositing a photoresist layer on an upper surface of the SiO 2 layer; patterning the photoresist layer to define a predetermined plurality of areas for deposition of a second semiconductor material having a second type of conductivity into the first semiconductor materials, the second type of conductivity being different from the first type of conductivity; etching the SiO 2 along the areas defined in the photoresist to form trenches in the SiO 2 layer separated by SiO 2 mesas; removing the photoresist and further etching the trenches in the SiO 2 layer so as to extend the trenches into the a-Si/poly Si layer; etching each trench within the a-Si/poly-Si layer to form an undercut beneath the SiO 2 material in each trench; further etching the trenches with the formed undercut areas into the first semiconductor material layer to form trenches in the first semiconductor material; cleaning the trenches and the undercut areas to remove physical and chemical damage caused during etching; forming a contact layer on a backside of the first semiconductor material layer; depositing a layer of the second semiconductor material into the trenches in the first semiconductor material layer, a thickness of the second semiconductor material in the first semiconductor material being sufficient to fill the trenches and form filled trenches of the second semiconductor material, the filled trenches having the second type of conductivity within the first semiconductor material a location, width, and separation of the filled trenches being defined by the patterning of the photoresist; further etching the a-Si/poly-Si layer to remove any remaining a-Si/poly-Si material not removed when the trenches were etched; removing the remaining SiO 2 with the deposited SiO 2 so that only the first semiconductor material layer with the filled trenches of the deposited second semiconductor material remain; and depositing a metal anode comprising a metal stack on an upper surface of the first semiconductor material layer with the filled trenches of the second semiconductor material, where the first semiconductor material serves as first type of contact to the metal anode and the second semiconductor material serves as a second type of contact to the metal anode.

2 . The method according to claim 1 , wherein the first semiconductor material has an n-type conductivity and the second semiconductor material has a p-type conductivity.

3 . The method according to claim 2 , wherein the first semiconductor material comprises Gallium Oxide, Germanium Oxide, Aluminum Oxide, Zinc Oxide, Indium Oxide, Tin Oxide, Cadmium Oxide, Scandium Oxide, Aluminum Nitride, Boron Nitride, Diamond, Aluminum Gallium Oxide (AGO), Lithium Gallium Oxide (LGO), Aluminum Zinc Oxide (AZO), Gallium Zinc Oxide (GZO), Indium Zinc Oxide (IZO), Indium Tin Oxide (ITO), Indium Tin Zirconium Oxide (ITZO), Indium Gallium Oxide (IGO), Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO), perovskite oxides, niobates, stannates, or vanadium oxides.

4 . The method according to claim 2 , wherein the second semiconductor material comprises Silicon, Gallium Arsenide, Gallium Nitride, Aluminum Gallium Nitride, Aluminum Nitride, Boron Nitride, binary or ternary Copper oxides, spinel oxides, perovskites, Nickel Oxide, Cuprous Iodide, or Diamond.

5 . The method according to claim 1 , wherein the first semiconductor material has a p-type conductivity and the second semiconductor material has an n-type conductivity.

6 . The method according to claim 5 , wherein the first semiconductor material comprises Silicon, Gallium Arsenide, Gallium Nitride, Aluminum Gallium Nitride, Aluminum Nitride, Boron Nitride, binary or ternary Copper oxide, spinel oxide, perovskites, Nickel Oxide, Cuprous Iodide, or Diamond.

7 . The method according to claim 5 , wherein the second semiconductor material comprises Gallium Oxide, Germanium Oxide, Aluminum Oxide, Zinc Oxide, Indium Oxide, Tin Oxide, Cadmium Oxide, Scandium Oxide, Aluminum Nitride, Boron Nitride, Diamond, or ternary and quaternary compounds of the aforementioned oxides such as Aluminum Gallium Oxide (AGO), Lithium Gallium Oxide (LGO), Aluminum Zinc Oxide (AZO), Gallium Zinc Oxide (GZO), Indium Zinc Oxide (IZO), Indium Tin Oxide (ITO), Indium Tin Zirconium Oxide (ITZO), Indium Gallium Oxide (IGO), Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO), perovskite oxides, niobates, stannates, or vanadium oxides.

8 . The method according to claim 1 , wherein the first semiconductor material is n-type Ga 2 O 3 and the second semiconductor material is p-type NiO; and
wherein the metal anode creates a Schottky contact to the n-type Ga 2 O 3 material and as an Ohmic contact to the p-type NiO in the NiO-filled trenches.

9 . The method according to claim 1 , wherein the filled trenches within the first semiconductor material layer have a width of about 2.2 μm and are spaced about 1.7 μm apart.

10 . The method according to claim 1 , further comprising depositing a Ni layer between the SiO 2 layer and the photoresist, the Ni layer forming a hard mask for the etching of the trenches for deposition of the second semiconductor material into the first semiconductor material.

Assignees

• Us Gov Sec Navy

Inventors

• Spencer Joseph A
• Tadjer Marko J
• Jacobs Alan G
• Hobart Karl D
• Zhang Yuhao

Classifications

• H10D8/605

  of the trench conductor-insulator-semiconductor barrier type, e.g. trench MOS barrier Schottky rectifiers [TMBS] · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D8/051 Primary

  of Schottky diodes · CPC title