Method of manufacturing capacitor, capacitor, and memory

Patent metadata

Field	Value
Publication number	US-12513879-B2
Application number	US-202217822815-A
Country	US
Kind code	B2
Filing date	Aug 29, 2022
Priority date	Apr 29, 2022
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

The present disclosure provides a method of manufacturing a capacitor, a capacitor, and a memory, and relates to the technical field of semiconductors. The method of manufacturing a capacitor includes: providing a substrate; forming a first electrode on the substrate, the first electrode extending in a first direction parallel to the substrate, a size of the first electrode in the first direction being greater than a size of the first electrode in a second direction and a size of the first electrode in a third direction, and every two of the first direction, the second direction, and the third direction being perpendicular to each other; forming a dielectric layer wrapping the first electrode; and forming a second electrode wrapping the dielectric layer.

First claim

The invention claimed is:

1 . A method of manufacturing a capacitor, comprising:
providing a substrate; forming a first electrode on the substrate, the first electrode extending in a first direction parallel to the substrate, a size of the first electrode in the first direction being greater than a size of the first electrode in a second direction and a size of the first electrode in a third direction, and every two of the first direction, the second direction, and the third direction being perpendicular to each other, wherein the forming the first electrode on the substrate comprises: forming at least one epitaxial layer on the substrate, the epitaxial layer comprising a monocrystalline layer and a silicon-containing material layer arranged in a stacked manner, and a size of the monocrystalline layer in the first direction being greater than a size of the monocrystalline layer in the second direction and a size of the monocrystalline layer in the third direction; defining a pattern region and a contact region on the epitaxial layer, wherein a portion of the monocrystalline layer in the contact region forms a source region or a drain region of a transistor; selectively etching the epitaxial layer downwards in the pattern region until the substrate is exposed, a remaining portion of the epitaxial layer in the pattern region defining a position of the first electrode and extending transversely, wherein a remaining portion of the monocrystalline layer reserves a gap for the first electrode; removing the remaining portion of the monocrystalline layer in the remaining portion of the epitaxial layer in the pattern region, and forming the gap; and forming the first electrode in the gap; forming a dielectric layer wrapping the first electrode; and forming a second electrode wrapping the dielectric layer.

2 . The method of manufacturing a capacitor according to claim 1 , further comprising:
forming a plurality of first electrodes arranged at intervals at least one of in the second direction or in the third direction, a three-dimensional space being formed between adjacent two of the first electrodes; the dielectric layer wrapping surfaces of the plurality of first electrodes and being located in the three-dimensional space, and forming a common dielectric layer; and the second electrode wrapping a surface of the dielectric layer and being located in the three-dimensional space, and forming a common second electrode.

3 . The method of manufacturing a capacitor according to claim 1 , wherein a patterned first mask layer is formed on the epitaxial layer, and the epitaxial layer is etched downwards by taking the patterned first mask layer as a mask until the substrate is exposed, to synchronously define the pattern region, the contact region, and the position of the first electrode.

4 . The method of manufacturing a capacitor according to claim 1 , wherein the forming the first electrode in the gap comprises:
depositing a first electrode material in the pattern region, the first electrode material filling up a groove in the pattern region and the gap, extending outside the pattern region, and covering a top surface of the contact region; and removing a portion of the first electrode material in the groove and on the top surface of the contact region by a maskless etching, a remaining portion of the first electrode material in the gap forming the first electrode.

5 . The method of manufacturing a capacitor according to claim 4 , wherein the first electrode material is formed by using both an atomic layer deposition process and a chemical vapor deposition process.

6 . The method of manufacturing a capacitor according to claim 1 , after the forming the first electrode in the gap, the method of manufacturing a capacitor further comprises: forming a support structure on a side wall of the first electrode; and the forming a support structure on a side wall of the first electrode comprises:
depositing a support material in the pattern region, the support material extending outside the pattern region and covering a top surface of the contact region; forming a patterned second mask layer on a surface of the support material, the patterned second mask layer covering a surface of the contact region and further forming an array arrangement in the pattern region; etching the support material downwards by taking the patterned second mask layer as a mask until the epitaxial layer is exposed, to form an array opening in the pattern region; continuing etching the support material downwards along the array opening until the substrate is exposed; and removing a portion of the support material by a top surface height such that a remaining portion of the support material is located on the side wall of the first electrode and a side wall of the contact region, and forming the support structure.

7 . The method of manufacturing a capacitor according to claim 1 , when a plurality of first electrodes are formed, the method of manufacturing a capacitor further comprises:
removing a portion of the silicon-containing material layer in the remaining portion of the epitaxial layer in the pattern region by using a wet etching process or a steam etching process, to form a three-dimensional space.

8 . The method of manufacturing a capacitor according to claim 1 , wherein the forming a dielectric layer wrapping the first electrode comprises:
forming the dielectric layer by using an atomic layer deposition process, the dielectric layer continuously wrapping a surface of the first electrode.

9 . The method of manufacturing a capacitor according to claim 1 , wherein the forming a second electrode layer wrapping the dielectric layer comprises:
forming the second electrode layer by using an atomic layer deposition process, the second electrode layer continuously wrapping an outer surface of the dielectric layer.

10 . The method of manufacturing a capacitor according to claim 1 , wherein the first electrode has an aspect ratio between the first direction and the third direction, and the aspect ratio is greater than or equal to 35.

11 . The method of manufacturing a capacitor according to claim 1 , wherein the capacitor is connected to a gate-all-around transistor, a gate of the gate-all-around transistor is connected to a word line, one of a drain and a source of the gate-all-around transistor is connected to a bit line, the other one of the drain and the source of the gate-all-around transistor is connected to the first electrode of the capacitor, the first electrode extends in the first direction, the word line extends in the second direction, and the bit line extends in the third direction.

Assignees

• Changxin Memory Tech Inc
• Changxin Jidian Beijing Memory Tech Co Ltd

Inventors

• Yang Mengmeng
• Xiao Deyuan

Classifications

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title