Apparatus, method and recording medium for digital clock and data recovery

Patent metadata

Field	Value
Publication number	US-12512840-B2
Application number	US-202418420807-A
Country	US
Kind code	B2
Filing date	Jan 24, 2024
Priority date	May 25, 2023
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

Proposed is an apparatus for a digital clock and data recovery. The apparatus includes a frequency detector for detecting a high frequency (FH) signal, a low frequency (FL) signal and ultra-high frequency (FUH) signal by determining the relationship between an input data rate and a clock frequency, and generating a continuous frequency up (CFUP) signal and a continuous frequency down (CFDN) signal based on the FH, FL and FUH signals; and a digital loop filter (DLF) for controlling to adjust a clock frequency in a coarse adjustment stage using the CFUP and CFDN signals and to adjust a clock frequency in a fine adjustment stage using the FH and FL signals.

First claim

The invention claimed is:

1 . An apparatus for digital clock data recovery (CDR), comprising:
a frequency detector for detecting a high frequency (FH) signal, a low frequency (FL) signal and an ultra-high frequency (FUH) signal by determining a relationship between an input data rate and a clock frequency, and generating a continuous frequency up (CFUP) signal and a continuous frequency down (CFDN) signal based on the FH, FL and FUH signals; a digital loop filter (DLF) for adjusting the clock frequency in a coarse adjustment stage using the CFUP and CFDN signals and for adjusting the clock frequency in a fine adjustment stage using the FH and FL signals.

2 . The apparatus according to claim 1 , wherein the frequency detector generates the CFDN signal based on a HIGH signal blocked by a block signal and the FL signal which has passed through a NOT gate, and generates the CFUP signal based on the FL signal which has not passed through the NOT gate and the blocked HIGH signal which has passed through the NOT gate.

3 . The apparatus according to claim 1 , wherein the frequency detector includes a FH/FL detector for outputting a HIGH_SEL signal that converts the FUH signal into the FH signal when at least one of the FH signal and the FL signal is detected continuously in two or more sets, each set referring to 16 cycles of the clock.

4 . The apparatus according to claim 2 , wherein the frequency detector includes a block signal generator which outputs the block signal that blocks the HIGH signal and which is deactivated when the FL signal is not detected during a clock cycle.

5 . The apparatus according to claim 1 , further comprising a frequency lock detector for locking the clock frequency in the coarse adjustment stage if the FH signal occurs after a HIGH_SEL signal that converts the FUH signal to the FH signal is outputted and for locking the clock frequency in the fine adjustment stage if an UP0 signal or a DN0 signal remains at 0 (LOW) or the FL signal is detected, during a clock cycle.

6 . The apparatus according to claim 1 , wherein the frequency detector detects the FH signal when the clock frequency is higher than the input data rate, detects the FL signal when the clock frequency is lower than the input data rate, and detects the FUH signal when the clock frequency is higher than a multiple of input data rate.

7 . A method for digital clock data recovery (CDR), comprising the steps of:
detecting, by a frequency detector, a high frequency (FH) signal, a low frequency (FL) signal and an ultra-high frequency (FUH) signal by determining a relationship between an input data rate and a clock frequency; generating, by the frequency detector, a continuous frequency up (CFUP) signal and a continuous frequency down (CFDN) signal based on the FH, FL and FUH signals; and adjusting, by a digital loop filter (DLF), a clock frequency in a coarse adjustment stage using the CFUP and CFDN signals and a clock frequency in a fine adjustment stage using the FH and FL signals.

8 . The method according to claim 7 , wherein the step of generating, by the frequency detector, the CFUP and CFDN signals includes generating the CFDN signal based on a HIGH signal blocked by a block signal and the FL signal which has passed through a NOT gate, and generating the CFUP signal based on the FL signal which has not passed through the NOT gate and the blocked HIGH signal which has passed through the NOT gate.

9 . The method according to claim 7 , further comprising the step of outputting, by a FH/FL detector, a HIGH_SEL signal that converts the FUH signal into the FH signal when at least one of the FH signal and the FL signal is detected continuously in two or more sets, each set referring to 16 cycles of the clock.

10 . The method according to claim 8 , wherein the step of generating, by the frequency detector, the CFUP and CFDN signals includes outputting, by a block signal generator, the block signal that blocks the HIGH signal and deactivating the block signal generator when the FL signal is not detected during a clock cycle.

11 . The method according to claim 7 , further comprising the step of locking, by a frequency lock detector, the clock frequency in the coarse adjustment stage if the FH signal occurs after a HIGH_SEL signal that converts the FUH signal to the FH signal is outputted and the clock frequency in the fine adjustment stage if an UP0 signal or a DN0 signal remains at 0 (LOW) or the FL signal is detected, during a clock cycle.

12 . The method according to claim 7 , wherein the step of detecting, by the frequency detector, the FH, FL and FUH signals includes detecting the FH signal when the clock frequency is higher than the input data rate, detecting the FL signal when the clock frequency is lower than the input data rate, and detecting the FUH signal when the clock frequency is higher than a multiple of the input data rate.

13 . A non-transitory recording medium on which a computer program for performing the method of claim 7 is recorded.

Assignees

• Found Res & Business Seoul Nat Univ Sci & Tech

Inventors

• Lee Won Young
• Lee Hyun Bin

Classifications

• H04L7/02

  Speed or phase control by the received code signals, the signals containing no special synchronisation information {(H04L7/0075 takes precedence)} · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/095

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title