Analog in-memory discrete signal processor with minimum usage of ADC

Patent metadata

Field	Value
Publication number	US-12512154-B2
Application number	US-202318332572-A
Country	US
Kind code	B2
Filing date	Jun 9, 2023
Priority date	Jun 9, 2023
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

The present disclosure provides for a semiconductor device with integrated sensing and processing functionalities. The semiconductor device includes a sensing module configured to generate a plurality of analog sensing signals; and a machine learning (ML) processor. The sensing module and the ML processor are fabricated on a single wafer. The ML processor includes crossbar arrays that processes the analog sensing signals to generate analog preprocessed sensing data; an analog-to-digital converter (ADC) to convert the analog preprocessed sensing data into digital preprocessed sensing data; and a machine learning processing unit to process the digital preprocessed sensing data utilizing one or more machine learning model.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
at least one input node to receive an input electrical signal representative of an analog input signal; an analog signal processor, comprising:
one or more crossbar arrays configured to implement one or more circuits to process the input electrical signal representative of an analog input signal to generate processed analog signal data; and
a sample-and-hold (S/H) circuit to sample and hold a plurality of input signal values at varying points in time based on a configurable sampling rate, wherein the plurality of input signal values is provided as inputs to one or more crossbar arrays configured to implement at least one of a finite impulse response (FIR) filter, a discrete Fourier transform (DFT) filter, or a discrete wavelet transform (DWT) filter to generate an electrical signal in the time or frequency domain representative of the plurality of input signal values.

2 . The semiconductor device of claim 1 , wherein the electrical signal in the time or frequency domain is provided as an input to one or more crossbar arrays configured to implement at least one of a principal component analysis (PCA) and independent component analysis (ICA) circuit to perform blind source separation (BSS).

3 . The semiconductor device of claim 2 , wherein an output of the one or more crossbar arrays configured to implement at least one of a principal component analysis (PCA) and independent component analysis (ICA) circuit to perform blind source separation (BSS) is provided as an input to one or more crossbar arrays configured to implement at least one of a deep neural network (DNN), a convolutional neural network (CNN), or a recurrent neural network (RNN).

4 . The semiconductor device of claim 1 , wherein the electrical signal in the time or frequency domain is provided as an input to one or more crossbar arrays configured to implement a spectrum analyzer and noise suppressing circuit.

5 . The semiconductor device of claim 4 , wherein an output of the spectrum analyzer and noise suppressing circuit is provided as an input to one or more crossbar arrays configured to implement an inverse discrete Fourier transform (IDFT) circuit.

6 . The semiconductor device of claim 5 , wherein an output of the one or more crossbar arrays configured to implement the inverse discrete Fourier transform (IDFT) circuit is provided as an input to one or more crossbar arrays configured to implement at least one of a deep neural network (DNN), a convolutional neural network (CNN), or a recurrent neural network (RNN).

7 . The semiconductor device of claim 1 , wherein the input electrical signal, time domain signal (processed by FIR) or transformed signal by DCT or DWT is provided as an input to one or more crossbar arrays configured to implement at least one of a compressed sensing (CS) circuit, a sparse coding (SC) circuit.

8 . The semiconductor device of claim 1 , wherein the electrical signal in the frequency domain (Transformed by DFT) is provided as an input to one or more crossbar arrays configured to implement a Filter Bank (Fbank) circuit.

9 . The semiconductor device of claim 8 , wherein an output of the one or more crossbar arrays configured to implement at least one of a filter bank (Fbank) circuit is provided as an input to one or more crossbar arrays configured to implement a discrete cosine transform (DCT) circuit for feature extraction.

10 . The semiconductor device of claim 7 , wherein an output of the one or more crossbar arrays configured to implement at least one of a compressed sensing (CS) circuit, a sparse coding (SC) circuit, or a filter bank (Fbank) circuit is provided as an input to one or more crossbar arrays configured to implement at least one of a deep neural network (DNN), a convolutional neural network (CNN), or a recurrent neural network (RNN).

11 . The semiconductor device of claim 1 , further comprising at least one analog-to-digital converter communicatively coupled to the analog signal processor.

12 . A method, comprising:
receiving, in at least one input node, an input electrical signal representative of an analog input signal; processing, in an analog signal processor comprising one or more crossbar arrays configured to implement one or more circuits, the input electrical signal representative of an analog input signal to generate processed analog signal data; and sampling and holding, in a sample-and-hold (S/H) circuit, a plurality of input signal values at varying points in time based on a configurable sampling rate, wherein the plurality of input signal values is provided as inputs to one or more crossbar arrays configured to implement at least one of a finite impulse response (FIR) filter, a discrete Fourier transform (DFT) filter, or a discrete wavelet transform (DWT) filter to generate an electrical signal in the time or frequency domain representative of the plurality of input signal values.

13 . The method of claim 4 , wherein the electrical signal in the time or frequency domain is provided as an input to one or more crossbar arrays configured to implement at least one of a principal component analysis (PCA) and independent component analysis (ICA) circuit to perform blind source separation (BSS).

14 . The method of claim 13 , wherein an output of the one or more crossbar arrays configured to implement at least one of a principal component analysis (PCA) and independent component analysis (ICA) circuit to perform blind source separation (BSS) is provided as an input to one or more crossbar arrays configured to implement at least one of a deep neural network (DNN), a convolutional neural network (CNN), or a recurrent neural network (RNN).

15 . The method of claim 12 , wherein the electrical signal in the time or frequency domain is provided as an input to one or more crossbar arrays configured to implement a spectrum analyzer and noise suppressing circuit.

16 . A semiconductor device, comprising:
one or more sensor input devices to generate an input electrical signal representative of an analog signal; at least one input node to receive the input electrical signal representative of an analog input signal; and an analog signal processor, comprising one or more crossbar arrays configured to implement one or more circuits to process the input electrical signal representative of an analog input signal to generate processed analog signal data; and a sample-and-hold (S/H) circuit to sample and hold a plurality of input signal values at varying points in time based on a configurable sampling rate, wherein the plurality of input signal values is provided as inputs to one or more crossbar arrays configured to implement at least one of a finite impulse response (FIR) filter, a discrete Fourier transform (DFT) filter, or a discrete wavelet transform (DWT) filter to generate an electrical signal in the time or frequency domain representative of the plurality of input signal values.

17 . The semiconductor device of claim 16 , further comprising at least one analog-to-digital converter communicatively coupled to the analog signal processor.

Assignees

• Tetramem Inc

Inventors

• Hu Miao
• Wei Qiang

Classifications

• H03H17/02

  Frequency selective networks {(digital computers for complex mathematical operations G06F17/10)} · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G06N3/065

  Analogue means · CPC title