Refresh address counting circuit and method, refresh address read-write circuit and electronic device

Patent metadata

Field	Value
Publication number	US-12512141-B2
Application number	US-202318454104-A
Country	US
Kind code	B2
Filing date	Aug 23, 2023
Priority date	Aug 16, 2021
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

A refresh address counting circuit, a refresh address counting method, and a refresh address read-write circuit are provided. The refresh address counting circuit includes: a self-oscillation clock generation circuit, configured to generate, in each of refresh cycles, a self-oscillation clock signal based on at least one array activation signal upon acquiring a refresh signal; a self-oscillation mask circuit, configured to generate a self-oscillation mask signal under a preset refresh command; and a refresh address counter, configured to counting a refresh address based on the self-oscillation clock signal and the self-oscillation mask signal and to output a self-oscillation refresh address.

First claim

The invention claimed is:

1 . A refresh address counting circuit, comprising:
a self-oscillating clock generation circuit, configured to generate a self-oscillating clock signal based on at least one bank activation signal in each of refresh cycles, upon acquiring a refresh signal; a self-oscillating mask circuit configured to generate a mask signal under a preset refresh command; and a refresh address counter configured to count refresh addresses based on the self-oscillating clock signal and the mask signal and to output a self-oscillating refresh address; wherein the preset refresh command comprises a same-bank refresh command, an all-bank refresh command, or a self-refresh command; wherein the mask signal comprises: a mask sub-signal for masking the self-oscillating clock signal, and a non-mask sub-signal for not masking the self-oscillating clock signal; wherein the self-oscillating mask circuit comprises an all-bank refresh mask sub-circuit and a same-bank refresh mask sub-circuit, and wherein the all-bank refresh mask sub-circuit is configured to: in response to reception of the all-bank refresh command in a normal refresh mode, generate the mask sub-signal in a normal refresh mode when a lowest bit of a current refresh address is an odd number; and the same-bank refresh mask sub-circuit is configured to: in response to reception of the same-bank refresh command, generate the mask sub-signal before all banks are refreshed.

2 . The refresh address counting circuit of claim 1 , wherein the all-bank refresh mask sub-circuit is further configured to: in response to reception of the all-bank refresh command in the normal refresh mode, generate the non-mask sub-signal in the normal refresh mode when the lowest bit of the current refresh address is an even number.

3 . The refresh address counting circuit of claim 1 , wherein the all-bank refresh mask sub-circuit is further configured to turn off the mask sub-signal and generate the non-mask sub-signal in response to generating a system reset signal or receiving a cycle refresh command in the next refresh cycle.

4 . The refresh address counting circuit of claim 1 , wherein the same-bank refresh mask sub-circuit comprises a bank refresh counter, a reset signal generator, and a-mask signal generator, wherein
the bank refresh counter is configured to obtain a refresh state of each of banks, and generate a refresh cycle signal after each bank has been refreshed once; the mask signal generator is configured to generate the mask sub-signal or the non-mask sub-signal based on the refresh state of each bank; and the reset signal generator is configured to generate, based on the all-bank refresh command, a self-refresh command, a system reset signal and the refresh cycle signal, a reset signal for resetting the bank refresh counter to generate the non-mask sub-signal.

5 . The refresh address counting circuit of claim 4 , wherein the mask signal generator comprises a second NOT gate, a second NAND gate, and a second latch, wherein
a first input terminal of the second NAND gate is configured to receive the refresh cycle signal through the second NOT gate, a second input terminal of the second NAND gate is configured to receive the same-bank refresh command, and an output terminal of the second NAND gate is connected to a reset terminal of the second latch; and a set terminal of the second latch is configured to receive the reset signal, and an output terminal of the second latch is configured to output the mask signal.

6 . The refresh address counting circuit of claim 1 , wherein the self-oscillating clock generation circuit comprises an edge generation circuit and a delay circuit, and wherein
the edge generation circuit is configured to acquire each of the at least one bank activation signal in the refresh cycle, and extract falling edge information of the bank activation signal; and the delay circuit is configured to adjust timing of the falling edge information.

7 . A refresh address counting method, performed by a refresh address counting circuit including a self-oscillating clock generation circuit, a self-oscillating mask circuit, and a refresh address counter, the method comprising:
generating, by the self-oscillating clock generation circuit, a self-oscillating clock signal based on at least one bank activation signal in each of refresh cycles, upon acquiring a refresh signal; generating, by the self-oscillating mask circuit, a mask signal under a preset refresh command; and counting, by the refresh address counter, refresh addresses based on the self-oscillating clock signal and the mask signal and outputting, by the refresh address counter, a self-oscillating refresh address; wherein the preset refresh command comprises a same-bank refresh command, an all-bank refresh command, or a self-refresh command; the mask signal comprises: a mask sub-signal for masking the self-oscillating clock signal, and a non-mask sub-signal for not masking the self-oscillating clock signal; the self-oscillating mask circuit comprises an all-bank refresh mask sub-circuit and a same-bank refresh mask sub-circuit, and wherein generating, by the all-bank refresh mask sub-circuit, the mask sub-signal in a normal refresh mode when a lowest bit of a current refresh address is an odd number, in response to reception of the all-bank refresh command in a normal refresh mode; and generating, by the same-bank refresh mask sub-circuit, the mask sub-signal before all banks are refreshed in response to reception of the same-bank refresh command.

8 . A refresh address read-write circuit, comprising a latch circuit, a decoder, a reading circuit, and a refresh address counting circuit, wherein
an output terminal of the refresh address counting circuit is connected to an input terminal of the latch circuit, an output terminal of the latch circuit is connected to an input terminal of the decoder, and an output terminal of the decoder is connected to the reading circuit, and wherein the refresh address counting circuit includes: a self-oscillating clock generation circuit, configured to generate a self-oscillating clock signal based on at least one bank activation signal in each of refresh cycles, upon acquiring a refresh signal; a self-oscillating mask circuit, configured to generate a mask signal under a preset refresh command; and a refresh address counter, configured to count refresh addresses based on the self-oscillating clock signal and the mask signal and to output a self-oscillating refresh address.

9 . The refresh address read-write circuit of claim 8 , wherein the latch circuit comprises a multiplexer and a latch, and wherein
an input terminal of the multiplexer is configured to receive a self-oscillating refresh address and activation address from the refresh address counting circuit, a control terminal of the multiplexer is configured to receive a refresh cycle signal, an output terminal of the multiplexer is connected to an input terminal of the latch, and an output terminal of the latch is connected to the decoder.

Assignees

• Changxin Memory Tech Inc

Inventors

• Fan Xian
• Gu yinchuan
• Cao Xianlei
• Yang Yu
• Su Hsin-Cheng

Classifications

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title