Display device

Patent metadata

Field	Value
Publication number	US-12512060-B2
Application number	US-202418929137-A
Country	US
Kind code	B2
Filing date	Oct 28, 2024
Priority date	Dec 22, 2023
Publication date	Dec 30, 2025
Grant date	Dec 30, 2025

Abstract

A display device includes a display panel which includes a plurality of sub pixels; a first wiring line which transmits a first power voltage or a turn-off voltage to each of the plurality of sub pixels; a second wiring line which transmits a second power voltage or a reference voltage to each of the plurality of sub pixels; a third wiring line which transmits a data voltage or a sensing voltage to each of the plurality of sub pixels; a plurality of light emitting diodes which is connected to the first wiring line; a first transistor which is connected to the second wiring line; a second transistor which is connected to the second wiring line; and a third transistor which is connected to the third wiring line.

First claim

What is claimed is:

1 . A display device, comprising:
a display panel including a plurality of sub pixels; a first wiring line which transmits a first power voltage or a turn-off voltage to each of the plurality of sub pixels; a second wiring line which transmits a second power voltage or a reference voltage to each of the plurality of sub pixels; a third wiring line which transmits a data voltage or a sensing voltage to each of the plurality of sub pixels; a plurality of light emitting diodes which are disposed in each of the plurality of sub pixels, the plurality of light emitting diodes directly connected to the first wiring line; a first transistor in each of the plurality of sub pixels, the first transistor directly connected to the second wiring line; a second transistor in each of the plurality of sub pixels, the second transistor connected to the second wiring line; and a third transistor in each of the plurality of sub pixels, the third transistor connected to the third wiring line, wherein the plurality of light emitting diodes include a main light emitting diode and a redundancy light emitting diode.

2 . The display device according to claim 1 , wherein the plurality of light emitting diodes are connected to the first wiring line and a second node, the first transistor is connected to the second wiring line and a first node, the second transistor is connected to the second node and the second wiring line, the third transistor is connected to the third wiring line and the second node, and each of the plurality of sub pixels further includes a capacitor connected to the first node and the second node.

3 . The display device according to claim 2 , wherein when the first transistor is turned on, the first transistor electrically connects a gate electrode of the second transistor and the second wiring line.

4 . The display device according to claim 2 , wherein when the second transistor is turned on, the second transistor controls a driving current which flows from the second node to the second wiring line.

5 . The display device according to claim 2 , wherein when the third transistor is turned on, the third transistor electrically connects a source electrode of the second transistor and the third wiring line.

6 . The display device according to claim 2 , wherein the first transistor, the second transistor, and the third transistor are P-type transistors and anodes of the plurality of light emitting diodes are connected to the first wiring line.

7 . The display device according to claim 6 , wherein the first power voltage of the first wiring line is a high potential power voltage and the second power voltage of the second wiring line is a low potential power voltage.

8 . The display device according to claim 2 , wherein the first transistor, the second transistor, and the third transistor are N-type transistors and cathodes of the plurality of light emitting diodes are connected to the first wiring line.

9 . The display device according to claim 8 , wherein the first power voltage of the first wiring line is a low potential power voltage and the second power voltage of the second wiring line is a high potential power voltage.

10 . The display device according to claim 2 , further comprising:
a data driver connected to the third wiring line, wherein the data driver includes:
an analog-digital converter;
a first control transistor which is configured to transmit the data voltage and the sensing voltage to the third wiring line;
a second control transistor which is connected to the analog-digital converter and the third wiring line; and
a line capacitor connected to the third wiring line.

11 . The display device according to claim 10 , wherein each of the plurality of sub pixels is driven in an order of a data writing period and an emission period, and during the data writing period, the first wiring line transmits the turn-off voltage to each of the plurality of sub pixels, the second wiring line transmits the second power voltage to each of the plurality of sub pixels, and the third wiring line transmits the data voltage to each of the plurality of sub pixels.

12 . The display device according to claim 11 , wherein during the emission period, the first wiring line transmits the first power voltage to each of the plurality of sub pixels and the second wiring line transmits the second power voltage to each of the plurality of sub pixels.

13 . The display device according to claim 11 , wherein a sensing period when a threshold voltage of the second transistor of each of the plurality of sub pixels is sensed when a power of the display device is turned off is further provided and during the sensing period, the first wiring line transmits the turn-off voltage to each of the plurality of sub pixels and the second wiring line transmits the reference voltage to each of the plurality of sub pixels.

14 . The display device according to claim 13 , wherein during a partial period of the sensing period, the third wiring line transmits the sensing voltage to each of the plurality of sub pixels.

15 . The display device according to claim 14 , wherein during the data writing period and the emission period, the first control transistor is turned on and the second control transistor is turned off, during a partial period of the sensing period, the first control transistor is turned on and the second control transistor is turned off, and during a remaining period of the sensing period, the first control transistor is turned off and the second control transistor is turned on.

Assignees

• Lg Display Co Ltd

Inventors

• Seo Daeyoung
• Lee Byunghyun
• Kim Minseok
• Kim Taeyong
• Lee Sumin

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0465

  Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09G2330/02

  Details of power systems and of start or stop of display operation · CPC title