Phase change memory device wherein first and second electrodes penetrate through dielectric and phase change layers

Patent metadata

Field	Value
Publication number	US-12507600-B2
Application number	US-202217873166-A
Country	US
Kind code	B2
Filing date	Jul 26, 2022
Priority date	Jul 26, 2022
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

A memory device includes a substrate, a first signal line, a first dielectric layer, a phase change layer, a second dielectric layer, a first electrode, a second electrode and a second signal line. The first signal line is disposed over the substrate. The first dielectric layer is disposed over the first signal line. The phase change layer is disposed over the first dielectric layer. The second dielectric layer is disposed over the phase change layer. The first electrode and the second electrode are penetrating through the first dielectric layer, the phase change layer and the second dielectric layer, wherein the phase change layer is located between the first electrode and the second electrode. The second signal line is disposed over the second dielectric layer, wherein the first signal line is electrically connected with the first electrode, and the second signal line is electrically connected with the second electrode.

First claim

What is claimed is:

1 . A memory device, comprising:
a substrate; a first signal line over the substrate; a first dielectric layer over the first signal line; a first insulation layer disposed between the first dielectric layer and the substrate, wherein the first signal line is located in the first insulation layer; a phase change layer over the first dielectric layer; a second dielectric layer over the phase change layer; a first electrode and a second electrode penetrating through the first dielectric layer, the phase change layer and the second dielectric layer, wherein the phase change layer is located between a sidewall of the first electrode and a sidewall of the second electrode, and a bottom surface of the second electrode is in direct contact with the first insulation layer; and a second signal line over the second dielectric layer, wherein the first signal line is electrically connected with the first electrode, and the second signal line is electrically connected with the second electrode.

2 . The memory device according to claim 1 , wherein each of the first dielectric layer, the phase change layer and the second dielectric layer are surrounding the first electrode and the second electrode, and each of the first dielectric layer, the phase change layer and the second dielectric layer are in contact with the sidewall of the first electrode and the sidewall of the second electrode.

3 . The memory device according to claim 1 , further comprising:
a second insulation layer disposed above the second dielectric layer, wherein the second signal line is located in the second insulation layer, wherein a top surface of the first electrode is in contact with the second insulation layer, a top surface of the second electrode is in contact with the second signal line, and a bottom surface of the first electrode is in contact with the first signal line.

4 . The memory device according to claim 1 , wherein the first signal line is parallel to the second signal line.

5 . The memory device according to claim 4 , wherein the first signal line and the second signal line are extending along a first direction, and the first electrode and the second electrode are arranged along a second direction not parallel to the first direction.

6 . The memory device according to claim 1 , further comprising:
a top electrode disposed between the second signal line and the second electrode.

7 . A memory device, comprising:
a substrate; a first insulation layer over the substrate; first signal lines in the first insulation; a first dielectric layer over the first signal lines; a phase change layer; a second dielectric layer, wherein the phase change layer is located between the first dielectric layer and the second dielectric layer; first electrodes and second electrodes located in the first dielectric layer, the phase change layer and the second dielectric layer, wherein the phase change layer is surrounding the first electrodes and the second electrodes; a second insulation layer over the second dielectric layer, wherein top surfaces of the first electrodes are in direct contact with the second insulation layer; and second signal lines in the second insulation layer, wherein the first signal lines are electrically connected with the first electrodes, and the second signal lines are electrically connected with the second electrodes.

8 . The memory device according to claim 7 , wherein the phase change layer comprises a first portion and a second portion separated from the first portion, a part of the first electrodes and a part of the second electrodes are penetrating through the first portion, and another part of the first electrodes and another part of the second electrodes are penetrating through the second portion.

9 . The memory device according to claim 8 , wherein the first signal lines and the second signal lines are extending along a first direction, and the part of the first electrodes and the part of the second electrodes are alternately arranged along a second direction not parallel to the first direction.

10 . The memory device according to claim 8 , wherein the first signal lines and the second signal lines are extending along a first direction, and the first portion and the second portion are extending along a second direction not parallel to the first direction.

11 . The memory device according to claim 7 , wherein bottom surfaces of the first electrodes are in contact with the first signal lines, bottom surfaces of the second electrodes are in contact with the first insulation layer, and top surfaces of the second electrodes are in contact with the second signal lines.

12 . The memory device according to claim 7 , wherein the phase change layer is in contact with sidewalls of the first electrodes and sidewalls of the second electrodes.

13 . The memory device according to claim 12 , wherein the first dielectric layer and the second dielectric layer are in contact with the sidewalls of the first electrodes and the sidewalls of the second electrodes.

14 . A fabrication method of a memory device, comprising:
forming a first insulation layer and a first signal line located in the first insulation layer over a substrate; forming a first dielectric layer over the first signal line, wherein the first insulation layer is disposed between the first dielectric layer and the substrate; forming a phase change layer over the first dielectric layer; forming a second dielectric layer over the phase change layer; forming a first opening and a second opening penetrating through the first dielectric layer, the phase change layer and the second dielectric layer, wherein the first signal line is exposed by the first opening; forming a first electrode and a second electrode penetrating through the first dielectric layer, the phase change layer and the second dielectric layer, wherein the first electrode is located in the first opening and electrically connected with the first signal line, and the second electrode is located in the second opening, wherein the phase change layer is located between a sidewall of the first electrode and a sidewall of the second electrode, and a bottom surface of the second electrode is in direct contact with the first insulation layer; and forming a second signal line over the second dielectric layer and the second electrode, wherein the second signal line is electrically connected with the second electrode.

15 . The fabrication method according to claim 14 , wherein a method of forming the first electrode and the second electrode comprises:
forming a conductive material layer over the second dielectric layer, wherein the conductive material layer is filling into the first opening and the second opening; and removing a portion of the conductive material layer outside the first opening and the second opening.

16 . The fabrication method according to claim 14 , further comprising:
patterning the phase change layer before forming the second dielectric layer.

17 . The fabrication method according to claim 14 , wherein the first opening and the second opening are formed in one or more etching process using a same mask.

18 . The fabrication method according to claim 17 , wherein
the first insulation layer is exposed by the second opening before forming the second electrode.

19 . The fabrication method according to claim 18 , wherein the last one in one or more etching process is etching stop at the first signal line and the first insulation layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semicondcutor Mfg Company Ltd

Inventors

• Lin yu-chao
• Chiu Jung-Piao
• Yu Shao-Ming
• Tu Yuan-Tien
• Lee Tung-Ying

Classifications

• H10N70/826

  adapted for essentially vertical current flow, e.g. sandwich or pillar type devices · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title

• H10N70/841

  Electrodes · CPC title

• H10B63/80

  Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays · CPC title

• H10B63/10

  Phase change RAM [PCRAM, PRAM] devices · CPC title