Gate-all-around integrated circuit structures having necked feature

Patent metadata

Field	Value
Publication number	US-12507449-B2
Application number	US-202217700215-A
Country	US
Kind code	B2
Filing date	Mar 21, 2022
Priority date	Mar 21, 2022
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Gate-all-around integrated circuit structures having necked features, and methods of fabricating gate-all-around integrated circuit structures having necked features, are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires. Each nanowire of the vertical stack of horizontal nanowires has a channel portion with a first vertical thickness and has end portions with a second vertical thickness greater than the first vertical thickness. A gate stack is surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a vertical stack of horizontal nanowires, each nanowire of the vertical stack of horizontal nanowires having a channel portion with a first vertical thickness and having end portions with a second vertical thickness greater than the first vertical thickness; a gate stack surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires; and a spacer structure surrounding each of the end portions of each nanowire of the vertical stack of horizontal nanowires, wherein the spacer structure is vertically overlapping with a portion of the gate stack.

2 . The integrated circuit structure of claim 1 , wherein the gate stack comprises a layer of an oxide of the channel portion, a high-k gate dielectric layer, and a gate electrode.

3 . The integrated circuit structure of claim 1 , further comprising source or drain structures coupled to the end portions of each nanowire of the vertical stack of horizontal nanowires.

4 . The integrated circuit structure of claim 1 , further comprising:
a second vertical stack of horizontal nanowires, each nanowire of the second vertical stack of horizontal nanowires having a channel portion with a third vertical thickness and having end portions with a fourth vertical thickness greater than the third vertical thickness, wherein the fourth vertical thickness is greater than the third vertical thickness by an amount different than an amount that the second vertical thickness is greater than the first vertical thickness, and wherein the second vertical stack of horizontal nanowires has a threshold voltage different than a threshold voltage of the vertical stack of horizontal nanowires; and a second gate stack surrounding the channel portion of each nanowire of the second vertical stack of horizontal nanowires.

5 . A method of fabricating an integrated circuit structure, the method comprising:
forming a vertical arrangement of nanowires, each nanowire of the vertical stack of horizontal nanowires having a channel portion with a first vertical thickness and having end portions with a second vertical thickness greater than the first vertical thickness; forming a permanent gate stack surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires; forming a spacer structure surrounding each of the end portions of each nanowire of the vertical stack of horizontal nanowires, wherein the spacer structure is vertically overlapping with a portion of the gate stack; and forming a first epitaxial source or drain structure at a first end of the vertical arrangement of nanowires, and forming a second epitaxial source or drain structure at a second end of the vertical arrangement of nanowires.

6 . The method of claim 5 , wherein forming the permanent gate stack comprises removing a dummy gate electrode from over an initial vertical arrangement of nanowires, etching channel regions of the initial vertical arrangement of nanowires to form the vertical arrangement of nanowires, and then forming the permanent gate stack surrounding the etched channel regions.

7 . The method of claim 6 , further comprising releasing the vertical arrangement of nanowires from a sacrificial material subsequent to removing the dummy gate electrode and prior to forming the permanent gate stack.

8 . The method of claim 5 , wherein the first and second epitaxial source or drain structures are formed prior to forming the permanent gate stack.

9 . The method of claim 5 , wherein the first and second epitaxial source or drain structures are formed subsequent to forming the permanent gate stack.

10 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure comprising:
a vertical stack of horizontal nanowires, each nanowire of the vertical stack of horizontal nanowires having a channel portion with a first vertical thickness and having end portions with a second vertical thickness greater than the first vertical thickness;
a gate stack surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires; and
a spacer structure surrounding each of the end portions of each nanowire of the vertical stack of horizontal nanowires, wherein the spacer structure is vertically overlapping with a portion of the gate stack.

11 . The computing device of claim 10 , further comprising:
a memory coupled to the board.

12 . The computing device of claim 10 , further comprising:
a communication chip coupled to the board.

13 . The computing device of claim 10 , further comprising:
a battery coupled to the board.

14 . The computing device of claim 10 , wherein the component is a packaged integrated circuit die.

15 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure formed according to a method comprising:
forming a vertical arrangement of nanowires, each nanowire of the vertical stack of horizontal nanowires having a channel portion with a first vertical thickness and having end portions with a second vertical thickness greater than the first vertical thickness;
forming a permanent gate stack surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires;
forming a spacer structure surrounding each of the end portions of each nanowire of the vertical stack of horizontal nanowires, wherein the spacer structure is vertically overlapping with a portion of the gate stack; and
forming a first epitaxial source or drain structure at a first end of the vertical arrangement of nanowires, and forming a second epitaxial source or drain structure at a second end of the vertical arrangement of nanowires.

16 . The computing device of claim 15 , further comprising:
a memory coupled to the board.

17 . The computing device of claim 15 , further comprising:
a communication chip coupled to the board.

18 . The computing device of claim 15 , further comprising:
a battery coupled to the board.

19 . The computing device of claim 15 , wherein the component is a packaged integrated circuit die.

20 . An integrated circuit structure, comprising:
a vertical stack of horizontal nanowires, each nanowire of the vertical stack of horizontal nanowires having a channel portion with a first vertical thickness and having end portions with a second vertical thickness greater than the first vertical thickness; a gate stack surrounding the channel portion of each nanowire of the vertical stack of horizontal nanowires; a second vertical stack of horizontal nanowires, each nanowire of the second vertical stack of horizontal nanowires having a channel portion with a third vertical thickness and having end portions with a fourth vertical thickness greater than the third vertical thickness, wherein the fourth vertical thickness is greater than the third vertical thickness by an amount different than an amount that the second vertical thickness is greater than the first vertical thickness, and wherein the second vertical stack of horizontal nanowires has a threshold voltage different than a threshold voltage of the vertical stack of horizontal nanowires; and a second gate stack surrounding the channel portion of each nanowire of the second vertical stack of horizontal nanowires.

Assignees

• Intel Corp

Inventors

• Mehandru Rishabh
• Weber Cory
• Mishra Varun
• Ghani Tahir
• Patel Pratik
• Chung Wonil
• Hasan Mohammad

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title