Adaptive biasing procedure to increase auxiliary PA efficiency for an integrated echo canceller

Patent metadata

Field	Value
Publication number	US-12506515-B2
Application number	US-202418618738-A
Country	US
Kind code	B2
Filing date	Mar 27, 2024
Priority date	Jan 9, 2024
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Techniques for echo cancellation in an RFID reader include incorporating an auxiliary error power amplifier (auxiliary PA) into the RFID reader, and dynamically adjusting a bias setting of the auxiliary PA based on a power level of a reflection of a signal transmitted by the RFID reader (“echo signal”) as measured at the RFID reader. When the measured echo signal power level is high, techniques herein set the auxiliary PA bias setting to a higher level to allow the auxiliary PA to account for the stronger echo signal. Inversely, when the measured echo signal power is low, techniques herein set the auxiliary PA bias setting to a lower level to reduce power consumption while the enabling the RFID reader to cancel echo phenomena and reliably detect signal responses from RFID tags in an environment.

First claim

What is claimed is:

1 . An echo cancellation assembly comprising:
a transceiver; a power amplifier; one or more processors; and one or more memories communicatively coupled to the one or more processors storing instructions that, when executed by the one or more processors, cause the assembly to: transmit, by the transceiver, an initial signal at a first power level and a first phase, measure a second power level and a second phase of a reflected signal, map the second power level to a bias setting of the power amplifier, determine, by an echo cancellation algorithm, an error vector signal with a third power level and a third phase that is at least partially out of phase relative to the second phase of the reflected signal, and drive the power amplifier at the bias setting to amplify the error vector signal and at least partially cancel the reflected signal.

2 . The echo cancellation assembly of claim 1 , wherein the instructions, when executed by the one or more processors, further cause the assembly to, subsequent to driving the power amplifier at the bias setting:
(a) measure a subsequent power level and a subsequent phase of a subsequent reflected signal; (b) determine, by the echo cancellation algorithm, a subsequent error vector signal with a subsequent power level and a subsequent phase that is at least partially out of phase with the subsequent phase of the reflected signal; (c) drive the power amplifier at the bias setting to amplify the subsequent error vector signal and at least partially cancel the subsequent reflected signal; and (d) iteratively repeat the actions (a), (b), and (c) until a minimum error threshold corresponding to the subsequent error vector signal is satisfied or a timeout threshold is exceeded.

3 . The echo cancellation assembly of claim 2 , wherein the bias setting of the power amplifier is maintained as a same bias setting throughout each of the actions (a), (b), (c), and (d).

4 . The echo cancellation assembly of claim 1 , wherein the power amplifier is an auxiliary power amplifier, wherein the assembly further comprises a primary power amplifier and an error vector modulator, and wherein the instructions, when executed by the one or more processors, further cause the assembly to:
determine, by the echo cancellation algorithm, at least one of an in-phase offset signal or a quadrature offset signal; and cause, by the echo cancellation algorithm, the error vector modulator to output the error vector signal based on one or more of (i) an error reference signal sampled at an output of the primary power amplifier, (ii) the in-phase offset signal, or (iii) the quadrature offset signal.

5 . The echo cancellation assembly of claim 1 , wherein the instructions, when executed by the one or more processors, further cause the assembly to determine, by the echo cancellation algorithm, the error vector signal by:
determining that the third power level of the error vector signal generates a minimum power level of the reflected signal; and identifying a convergence of the third power level of the error vector signal with the second power level of the reflected signal based on the minimum power level of the reflected signal.

6 . The echo cancellation assembly of claim 1 , further comprising a bandpass filter and an estimator, wherein the initial signal includes a pilot tone, the reflected signal includes a reflection of the pilot tone, and the instructions, when executed by the one or more processors, further cause the assembly to:
filter, by the bandpass filter, the reflected signal to detect the pilot tone; measure, by the estimator, a pilot power level and a pilot period of the pilot tone; generate, by the estimator, an error input based on the pilot power level and the pilot period; and determine, by the echo cancellation algorithm, the error vector signal based on the error input.

7 . The echo cancellation assembly of claim 6 , wherein the estimator generates the error input based on (i) an in-phase signal, (ii) a quadrature signal, or (iii) a combination of the in-phase signal and the quadrature signal.

8 . The echo cancellation assembly of claim 1 , further comprising:
an antenna module; and a circulator defining (i) a transmission signal path for the initial signal to reach the antenna module, and (ii) a reception signal path that transmits the reflected signal.

9 . A method comprising:
transmitting, by a transceiver, an initial signal at a first power level and a first phase; measuring a second power level and a second phase of a reflected signal; mapping the second power level to a bias setting of a power amplifier; determining, by an echo cancellation algorithm, an error vector signal with a third power level and a third phase that is at least partially out of phase relative to the second phase of the reflected signal; and driving the power amplifier at the bias setting to amplify the error vector signal and at least partially cancel the reflected signal.

10 . The method of claim 9 , further comprising, subsequent to driving the power amplifier at the bias setting:
(a) measuring a subsequent power level and a subsequent phase of a subsequent reflected signal; (b) determining, by the echo cancellation algorithm, a subsequent error vector signal with a subsequent power level and a subsequent phase that is at least partially out of phase with the subsequent phase of the reflected signal; (c) driving the power amplifier at the bias setting to amplify the subsequent error vector signal and at least partially cancel the subsequent reflected signal; and (d) iteratively repeating the actions (a), (b), and (c) until a minimum error threshold corresponding to the subsequent error vector signal is satisfied or a timeout threshold is exceeded.

11 . The method of claim 10 , wherein the bias setting of the power amplifier is maintained as a same bias setting throughout each of the actions (a), (b), (c), and (d).

12 . The method of claim 9 , wherein the power amplifier is an auxiliary power amplifier, and wherein the method further comprises:
determining, by the echo cancellation algorithm, at least one of an in-phase offset signal or a quadrature offset signal; and causing, by the echo cancellation algorithm, an error vector modulator to output the error vector signal based on one or more of (i) an error reference signal sampled at an output of a primary power amplifier, (ii) the in-phase offset signal, or (iii) the quadrature offset signal.

13 . The method of claim 9 , further comprising determining, by the echo cancellation algorithm, the error vector signal by:
determining that the third power level of the error vector signal generates a minimum power level of the reflected signal; and identifying a convergence of the third power level of the error vector signal with the second power level of the reflected signal based on the minimum power level of the reflected signal.

14 . The method of claim 9 , wherein the initial signal includes a pilot tone, the reflected signal includes a reflection of the pilot tone, and the method further comprises:
filtering, by a bandpass filter, the reflected signal to detect the pilot tone; measuring, by an estimator, a pilot power level and a pilot period of the pilot tone; generating, by the estimator, an error input based on the pilot power level and the pilot period; and determining, by the echo cancellation algorithm, the error vector signal based on the error input.

15 . The method of claim 14 , wherein the estimator generates the error input based on (i) an in-phase signal, (

Assignees

• Zebra Tech Corp

Inventors

• Demir Alpaslan
• Duron Mark W

Classifications

• G06K7/0008

  General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer · CPC title

• H03F1/3235

  using a pilot signal · CPC title

• H04B7/015 Primary

  Reducing echo effects · CPC title