Systems and methods for power management and control
US-11840150-B2 · Dec 12, 2023 · US
US12506432B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12506432-B2 |
| Application number | US-202318506454-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 10, 2023 |
| Priority date | Nov 10, 2023 |
| Publication date | Dec 23, 2025 |
| Grant date | Dec 23, 2025 |
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A vehicle system includes a first battery pack connected to a second battery pack via a flying capacitor multi-level inverter. The fling capacitor inverter has multiple inverter legs, with each inverter leg being arranged in a flying capacitor topology. A three phase motor is connected to the inverter. A controller connected to the motor and the inverter. The controller includes a memory storing instructions configured to cause the controller to control the inverter as a direct current (DC)-DC converter such that a circulating current passes through the motor, the first battery pack and the second battery pack.
Opening claim text (preview).
What is claimed is: 1 . A vehicle system comprising; a first battery pack connected to a second battery pack via a flying capacitor multi-level inverter having a plurality of inverter legs, with each inverter leg being arranged in a flying capacitor topology; a motor connected to the flying capacitor multi-level inverter, the motor having three phases; and a controller connected to the motor and the flying capacitor multi-level inverter, the controller including a memory storing instructions configured to cause the controller to control the flying capacitor multi-level inverter as a direct current (DC)-DC converter such that a circulating current passes through the motor, the first battery pack and the second battery pack. 2 . The vehicle system of claim 1 , wherein each inverter leg of the flying capacitor multi-level inverter comprises a first transistor connecting a positive bus to a high node a second transistor connecting the high node to an alternating (AC) output node, a third transistor connecting the AC output node to a low node, and a fourth transistor connecting the low node to a negative bus; and wherein each phase of the motor is connected to an AC output node of a corresponding inverter leg of the flying capacitor multi-level inverter. 3 . The vehicle system of claim 2 , wherein the motor is a four terminal motor, and wherein controlling the flying capacitor multi-level inverter as a DC-DC converter comprises: for each inverter leg, providing a first control signal to the first transistor and the fourth transistor, with the first control signal being inverted for the fourth transistor; providing a second control signal to the second transistor and third transistor of each inverter leg, with the second control signal being inverted for the third transistor, wherein the first control signals and the second control signals control an open/closed state of the first, second, third and fourth transistor of the corresponding inverter leg via Pulse Width Modulation (PWM); and wherein each first control signal is phase shifted from each other first control signal by 120 degrees and each second control signal is phase shifted from each other second control signal and second control signal by 120 degrees. 4 . The vehicle system of claim 2 , wherein the motor is a three terminal motor, and wherein controlling the flying capacitor multi-level inverter as a DC-DC converter comprises: for each of a first inverter leg and a second inverter leg, providing a first control signal to the first and fourth transistor of the corresponding inverter leg wherein the first control signal is inverted for the fourth transistor; providing a second control signal to the second and third transistor of the corresponding inverter leg, wherein the second control signal is inverted for the third transistor; wherein the first control signals and the second control signals control an open/closed state of the first, second, third and fourth transistor of the corresponding inverter legs via Pulse Width Modulation; wherein each first control signal is phase shifted from the other first control signal by 180 degrees and each second control signal is phase shifted from the other second control signal by 180 degrees; and providing a third control signal to the first, second, third and fourth transistor of the third inverter leg, the third control signal setting the first, second, third, and fourth transistor of the third inverter leg to off for a duration of controlling the multi-level inverter as the DC-DC converter. 5 . The vehicle system of claim 1 , wherein the first battery pack and the second battery pack are connected in parallel at one or both of a negative battery terminal and a positive battery terminal. 6 . The vehicle system of claim 1 , wherein the first battery pack and the second battery pack are connected in series via a common node, forming a series connected battery pack. 7 . The vehicle system of claim 6 , wherein a neutral node connects each phase of the motor to the common node. 8 . The vehicle system of claim 6 , wherein a first phase terminal of the of the motor is connected to the common node of the series connected battery pack. 9 . The vehicle system of claim 8 , wherein a first inverter leg is physically disposed closer to the first battery pack and closer to the second battery pack than each of a second inverter leg and a third inverter leg. 10 . The vehicle system of claim 1 , wherein the first battery pack comprises at least a first set of power cells and a second set of power cells connected to the first set of power cells at the low node. 11 . A method for transferring power between a first battery pack and a second battery pack of a vehicle system comprising: causing a controller to control a flying capacitor multi-level inverter as a direct current (DC)-DC converter such that a circulating current passes through the flying capacitor multi-level inverter, a motor, a first battery pack and a second battery pack, wherein the vehicle system comprises the first battery pack connected to the second battery pack via the flying capacitor multi-level inverter, the motor connected to the flying capacitor multi-level inverter; and a motor controller connected to the motor and the flying capacitor multi-level inverter, the motor controller including a memory storing instructions configured to cause the vehicle system to implement the method. 12 . The method of claim 11 , wherein the flying capacitor multi-level inverter includes three inverter legs, each inverter leg of the flying capacitor multi-level inverter comprising a first transistor connecting a positive bus to a high node a second transistor connecting the high node to an alternating current (AC) output node, a third transistor connecting the AC output node to a low node, and a fourth transistor connecting the low node to a negative bus; and wherein each phase of the motor is connected to the AC output node of a corresponding inverter leg. 13 . The method of claim 12 , wherein the motor is a four terminal motor, and wherein controlling the flying capacitor multi-level inverter as a DC-DC converter comprises: for each inverter leg, providing a first control signal to the first transistor and the fourth transistor, with the first control signal being inverted for the fourth transistor; providing a second control signal to the second transistor and third transistor of each inverter leg, with the second control signal being inverted for the third transistor; wherein the first control signals and the second control signals control an open/closed state of the first, second, third and fourth transistor of the corresponding inverter leg via Pulse Width Modulation; and wherein each first control signal is phase shifted from each other first control signal by 120 degrees, and each second control signal is phase shifted from each other second control signal by 120 degrees. 14 . The method of claim 12 , wherein the motor is a three terminal motor, and wherein controlling the multi-level inverter as a DC-DC converter comprises: for each of a first inverter leg and a second inverter leg, providing a first control signal to the first transistor and fourth transistor of the corresponding inverter leg wherein the first control signal is inverted for the fourth transistor, providing a second control signal to the second transistor and third transistor of the corresponding inverter leg, wherein the second control signal is inverted for the third transistor, the first control signals and the second control signals controlling an open/closed state of the first
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