Memory device, operation method thereof, and readable storage medium

Patent metadata

Field	Value
Publication number	US-12505893-B2
Application number	US-202418437123-A
Country	US
Kind code	B2
Filing date	Feb 8, 2024
Priority date	Sep 13, 2023
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Examples of present disclosure disclose a memory device and an operation method thereof, and a readable storage medium. The memory device includes: a first memory region and a second memory region, each including a plurality of memory cells; and a peripheral circuit coupled with the first memory region and the second memory region and configured to: when writing data to the first memory region, perform a first program operation on memory cells to be programmed in the first memory region by using first program voltages that increase gradually; and when writing data in the first memory region to the second memory region, perform a second program operation on memory cells to be programmed in the second memory region by using second program voltages that increase gradually.

First claim

What is claimed is:

1 . A memory device, comprising:
a first memory region and a second memory region, each of the first memory region and the second memory region comprising a plurality of memory cells; and a peripheral circuit coupled with the first memory region and the second memory region, wherein the peripheral circuit is configured to:
when writing data to the first memory region, perform a first program operation on memory cells to be programmed in the first memory region by using first program voltages that increase gradually, wherein there is a first difference between the first program voltages at two adjacent times; and
when writing data in the first memory region to the second memory region, perform a second program operation on memory cells to be programmed in the second memory region by using second program voltages that increase gradually, wherein there is a second difference between the second program voltages at two adjacent times;
wherein the second difference is less than the first difference.

2 . The memory device of claim 1 , wherein the peripheral circuit is configured to:
when the memory device is in an activated state, write data to the first memory region and perform the first program operation on the memory cells to be programmed in the first memory region; and when the memory device is in an idle state, write data in the first memory region to the second memory region and perform the second program operation on the memory cells to be programmed in the second memory region.

3 . The memory device of claim 1 , wherein a first program verify voltage of the first program operation is equal to a second program verify voltage of the second program operation.

4 . The memory device of claim 1 , wherein the first memory region comprises a plurality of first memory cells that store data by using a single-bit mode, and the second memory region comprises a plurality of second memory cells that store data by using a multi-bit mode.

5 . The memory device of claim 1 , wherein the first memory region comprises a faulty block, and the second memory region comprises a normal block.

6 . The memory device of claim 1 , wherein a proportion of garbage data in the first memory region is greater than a first preset proportion, and a proportion of garbage data in the second memory region is less than a second preset proportion.

7 . The memory device of claim 1 , wherein a number of program times of the memory cells in the first memory region is greater than a first preset number of times, and a number of program times of the memory cells in the second memory region is less than a second preset number of times.

8 . The memory device of claim 1 , wherein the peripheral circuit is configured to:
after writing the data in the first memory region to the second memory region, perform an erase operation on the first memory region.

9 . A memory device, comprising:
a memory region comprising a plurality of memory cells; and a peripheral circuit coupled with the memory region, wherein the peripheral circuit is configured to:
when the memory device is in an activated state, perform a first program operation on memory cells to be programmed in the memory region by using first program voltages that increase gradually, wherein there is a first difference between the first program voltages at two adjacent times; and
when the memory device is in an idle state, perform a second program operation on memory cells to be programmed in the memory region by using second program voltages that increase gradually, wherein there is a second difference between the second program voltages at two adjacent times;
wherein the second difference is less than the first difference.

10 . The memory device of claim 9 , wherein a first program verify voltage of the first program operation is equal to a second program verify voltage of the second program operation.

11 . An operation method of a memory device, comprising:
when writing data to a first memory region, performing a first program operation on memory cells to be programmed in the first memory region by using first program voltages that increase gradually, wherein there is a first difference between the first program voltages at two adjacent times; and when writing data in the first memory region to a second memory region, performing a second program operation on memory cells to be programmed in the second memory region by using second program voltages that increase gradually, wherein there is a second difference between the second program voltages at two adjacent times; wherein the second difference is less than the first difference.

12 . The operation method of claim 11 , wherein:
when the memory device is in an activated state, the data is written to the first memory region, the first program operation is performed on the memory cells to be programmed in the first memory region; and when the memory device is in an idle state, the data in the first memory region is written to the second memory region, the second program operation is performed on the memory cells to be programmed in the second memory region.

13 . The operation method of claim 11 , wherein a first program verify voltage of the first program operation is equal to a second program verify voltage of the second program operation.

14 . The operation method of claim 11 , wherein the first memory region comprises a plurality of first memory cells that store data by using a single-bit mode, and the second memory region comprises a plurality of second memory cells that store data by using a multi-bit mode.

15 . The operation method of claim 11 , wherein the first memory region comprises a faulty block, and the second memory region comprises a normal block.

16 . The operation method of claim 11 , wherein a proportion of garbage data in the first memory region is greater than a first preset proportion, and a proportion of garbage data in the second memory region is less than a second preset proportion.

17 . The operation method of claim 11 , wherein a number of program times of the memory cells in the first memory region is greater than a first preset number of times, and a number of program times of the memory cells in the second memory region is less than a second preset number of times.

18 . The operation method of claim 11 , further comprising:
after writing the data in the first memory region to the second memory region, performing an erase operation on the first memory region.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Chen Wenping
• Tian Yaoyao
• Li Da
• Qi Wei
• Zhang Shuai
• Tan Hua

Classifications

• G11C16/102 Primary

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title