Display panel having driver circuit with a plurality of shift registers and display device

Patent metadata

Field	Value
Publication number	US-12505808-B2
Application number	US-202418795787-A
Country	US
Kind code	B2
Filing date	Aug 6, 2024
Priority date	Aug 7, 2023
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Provided are a display panel and a display device which belong to the field of display technology. The display panel includes a driver circuit including a shift register, where the shift register includes an input circuit connected to at least an input signal terminal, a first clock signal line, and a first node; a control circuit connected to at least a first voltage signal line, a second voltage signal line, the first node, a second node, and a third node, where the first node and the third node are directly connected or connected through a first adjustment circuit; and an output circuit including a first output circuit and a second output circuit, where the first output circuit is connected to at least the first voltage signal line, the third node, and an output signal terminal.

First claim

What is claimed is:

1 . A display panel, comprising:
a base substrate, a driver circuit comprising a shift register, wherein the driver circuit is formed on the base substrate, and at least one of an initial input signal line configured to provide an initial input signal for the driver circuit or a power signal line configured to provide a power signal for a light-emitting element of the display panel, wherein the shift register comprises: an input circuit connected to at least an input signal terminal, a first clock signal line, and a first node; a control circuit connected to at least a first voltage signal line, a second voltage signal line, the first node, a second node, and a third node, wherein the first node and the third node are directly connected or connected through a first adjustment circuit, wherein the control circuit comprises a first control circuit and a second control circuit; the first control circuit comprises a first transistor, and the second control circuit comprises a second transistor; and an output circuit comprising, wherein the output circuit comprises a first output circuit and a second output circuit, the first output circuit is connected to at least the first voltage signal line, the third node, and an output signal terminal, and the second output circuit is connected to at least the second voltage signal line, the second node, and the output signal terminal; wherein at least one of the initial input signal line, the first clock signal line, the first voltage signal line, the second voltage signal line, or the power signal line is a preset signal line, the preset signal line is disposed on a side of a film where transistors of the driver circuit are located facing away from the base substrate, an n-type channel transistor of the first transistor and the second transistor is a preset transistor, and in a direction perpendicular to the base substrate, the preset signal line overlaps the preset transistor.

2 . The display panel according to claim 1 , wherein
the input circuit receives at least an input signal and a first clock signal and controls a signal of the first node; the control circuit receives at least a first voltage signal, a second voltage signal, the signal of the first node, and a signal of the third node and controls a signal of the second node; and the first output circuit receives at least the first voltage signal and the signal of the third node and controls an output signal, and the second output circuit receives at least the second voltage signal and the signal of the second node and controls the output signal.

3 . The display panel according to claim 2 , wherein
the first voltage signal is a logic low-level signal, and the second voltage signal is a logic high-level signal.

4 . The display panel according to claim 1 , wherein
the first control circuit is connected to at least the first voltage signal line, the second node, and the third node; and the second control circuit is connected to at least the second voltage signal line, the first node, and the second node.

5 . The display panel according to claim 4 , wherein
the first control circuit receives at least a first voltage signal and a signal of the third node and controls a signal of the second node; and the second control circuit receives at least a second voltage signal and a signal of the first node and controls the signal of the second node.

6 . The display panel according to claim 4 , wherein
a control terminal of the first control circuit is connected to the third node, and a control terminal of the second control circuit is connected to the first node; wherein when the first control circuit is turned on under control of a signal of the third node, the second control circuit is turned off under control of a signal of the first node; or when the first control circuit is turned off under control of a signal of the third node, the second control circuit is turned on under control of a signal of the first node.

7 . The display panel according to claim 4 , wherein
a first terminal of the first transistor is connected to the first voltage signal line, a second terminal of the first transistor is connected to the second node, and a control terminal of the first transistor is connected to the third node; and/or a first terminal of the second transistor is connected to the second voltage signal line, a second terminal of the second transistor is connected to the second node, and a control terminal of the second transistor is connected to the first node.

8 . The display panel according to claim 7 , wherein
when a signal of the third node controls the first transistor to be turned on, a signal of the first node controls the second transistor to be turned off; or when a signal of the third node controls the first transistor to be turned off, a signal of the first node controls the second transistor to be turned on.

9 . The display panel according to claim 7 , wherein
the first transistor and the second transistor have different types of channel regions.

10 . The display panel according to claim 7 , wherein
the first transistor is an n-type channel transistor, and the second transistor is a p-type channel transistor; or the first transistor is a p-type channel transistor, and the second transistor is an n-type channel transistor.

11 . The display panel according to claim 10 , wherein
an active layer of the first transistor comprises silicon, and an active layer of the second transistor comprises an oxide semiconductor; or an active layer of the first transistor comprises an oxide semiconductor, and an active layer of the second transistor comprises silicon.

12 . The display panel according to claim 11 , wherein
the first transistor comprises a first gate, a first active layer, a first source, and a first drain; the second transistor comprises a second gate, a second active layer, a second source, and a second drain; and the first active layer comprises silicon, and the second active layer comprises the oxide semiconductor; or the first active layer comprises the oxide semiconductor, and the second active layer comprises silicon.

13 . The display panel according to claim 12 , wherein
the first transistor further comprises a third gate, the first gate and the third gate are disposed on two sides of the first active layer separately, and the first active layer comprises the oxide semiconductor; or the second transistor further comprises a fourth gate, the second gate and the fourth gate are disposed on two sides of the second active layer separately, and the second active layer comprises the oxide semiconductor.

14 . The display panel according to claim 7 , wherein
a plurality of stages of shift registers of the driver circuit extend along a first direction; and the first transistor and the second transistor are arranged along the first direction.

15 . The display panel according to claim 7 , wherein
a plurality of stages of shift registers of the driver circuit extend along a first direction; and the first transistor and the second transistor are arranged along a second direction, wherein the first direction intersects with the second direction.

16 . The display panel according to claim 1 , wherein
in the direction perpendicular to the base substrate, the preset signal line overlaps at least one of the first transistor or the second transistor.

17 . The display panel according to claim 1 , wherein
a plurality of stages of shift registers of the driver circuit extend along a first direction;

Assignees

• Xiamen Tianma Display Tech Co Ltd

Inventors

• Hu Cheng
• Lai Qingjun

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title