Unidirectional counter

Patent metadata

Field	Value
Publication number	US-12505218-B2
Application number	US-202117336123-A
Country	US
Kind code	B2
Filing date	Jun 1, 2021
Priority date	Jun 1, 2021
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Apparatuses, systems, and techniques that implement a unidirectional counter with one-time-programmable memory that prevents the counter from reversing direction. In at least one embodiment, a unidirectional counter is implemented with a base value represented as a binary number and an offset represented as a bit field where each bit represents an equal amount.

First claim

What is claimed is:

1 . A computer system, comprising:
one or more processors; and one or more non-transitory machine-readable media storing executable instructions that, as a result of being executed by the one or more processors, cause the computer system to:
store a counter comprising a first bit field indicating a base value and a second bit field comprising a plurality of bits indicating an offset value to a memory;
modify at least one of the first bit field or the second bit field of the counter based, at least in part, on a software update provided to the computer system; and
install the software update to the computer system as a result of determining the software update is permitted to be installed,
wherein the first bit field and the second bit field are unable to be updated to a previous state, and the determination that the software update is permitted to be installed is based, at least in part, on an identification of at least one bit of the offset value that corresponds to the software update.

2 . The computer system of claim 1 , wherein the first bit field or the second bit field is stored in one or more one-time programmable memories.

3 . The computer system of claim 2 , wherein the one or more one-time programmable memories includes a programmable read-only memory (“PROM”), a FUSE memory, an erasable programmable read-only memory (“EPROM”), or an electrically erasable programmable read-only memory (“EEPROM”).

4 . The computer system of claim 2 , wherein the base value is represented as a multi-digit binary number.

5 . The computer system of claim 2 , wherein the offset value is represented as a second plurality of bits where each bit individually indicates whether a software update version is permitted to be installed.

6 . The computer system of claim 1 , wherein the one or more processors cannot change a bit stored in the first bit field or the second bit field from a one to a zero.

7 . The computer system of claim 6 , wherein a counter value stored cannot be less than a previous counter value stored.

8 . The computer system of claim 1 , wherein the one or more processors cannot change a storage bit in the first bit field or the second bit field from a zero to a one.

9 . The computer system of claim 8 , wherein a counter value stored cannot be greater than a previous counter value stored.

10 . The computer system of claim 1 , wherein a counter value is a sum of the base value in the first bit field and the offset value in the second bit field.

11 . A computer-implemented method comprising;
storing a counter comprising a first bit field indicating a base value and a second bit field comprising a plurality of bits indicating an offset value to a memory; and modifying at least one of the first bit field or the second bit field of the counter based, at least in part, on a software update provided to a computer system; and installing the software update to the computer system as a result of determining the software update is permitted to be installed, wherein the first bit field and the second bit field are unable to be updated to a previous state, and the determination that the software update is permitted to be installed is based, at least in part, on an identification of at least one bit of the offset value that corresponds to the software update.

12 . The computer-implemented method of claim 11 , wherein the first bit field or the second bit field is stored in one or more one-time programmable memories.

13 . The computer-implemented method of claim 12 , wherein the one or more one-time programmable memories includes a programmable read-only memory (“PROM”), a FUSE memory, an erasable programmable read-only memory (“EPROM”), or an electrically erasable programmable read-only memory (“EEPROM”).

14 . The computer-implemented method of claim 12 , wherein the base value is represented as a multi-digit binary number.

15 . The computer-implemented method of claim 12 , wherein the offset value is represented as a second plurality of bits where each bit individually indicates whether a software update version is permitted to be installed.

16 . The computer-implemented method of claim 11 , wherein a bit stored in the first bit field or the second bit field cannot be changed from a one to a zero.

17 . The computer-implemented method of claim 16 , wherein a counter value stored cannot be less than a previous counter value stored.

18 . The computer-implemented method of claim 11 , wherein a storage bit in the first bit field or the second bit field cannot be changed from a zero to a one.

19 . The computer-implemented method of claim 18 , wherein a counter value stored cannot be greater than a previous counter value stored.

20 . The computer-implemented method of claim 11 , wherein a counter value is a sum of the base value in the first bit field and the offset value in the second bit field.

21 . One or more non-transitory computer-readable storage media storing executable instructions that, as a result of being executed by one or more processors of a computer system, cause the computer system to:
store a counter comprising a first bit field indicating a base value and a second bit field comprising a plurality of bits indicating an offset value to a memory; and modify at least one of the first bit field or the second bit field of the counter based, at least in part, on a software update provided to the computer system; and install the software update to the computer system as a result of determining the software update is permitted to be installed, wherein the first bit field and the second bit field are unable to be updated to a previous state and the determination that the software update is permitted to be installed is based, at least in part, on an identification of at least one bit of the offset value corresponding to the software update indicates permission.

22 . The one or more non-transitory computer-readable storage media of claim 21 wherein the first bit field or the second bit field is stored in one or more one-time programmable memories.

23 . The one or more non-transitory computer-readable storage media of claim 22 wherein the one or more one-time programmable memories includes a programmable read-only memory (“PROM”), a FUSE memory, an erasable programmable read-only memory (“EPROM”), or an electrically erasable programmable read-only memory (“EEPROM”).

24 . The one or more non-transitory computer-readable storage media of claim 22 wherein the base value is represented as a multi-digit binary number.

25 . The one or more non-transitory computer-readable storage media of claim 22 wherein each bit of the offset value individually indicates a corresponding software update version to the computer system and the determination is based, at least in part, on a corresponding software update version indicated by the at least one bit of the offset value.

26 . The one or more non-transitory computer-readable storage media of claim 21 wherein the one or more processors cannot change a bit stored in the first bit field or the second bit field from a one to a zero.

27 . The one or more non-transitory computer-readable storage media of claim 26 , wherein a counter value stored cannot be less than a previous counter value stored.

28 . The one or more non-transitory computer-readable storage

Assignees

• Mellanox Technologies Ltd

Inventors

• Itkin Yuval
• Harel Guy
• Sfadia Mor

Classifications

• G06F8/66

  of program code stored in read-only memory [ROM] · CPC title

• G06F8/61

  Installation · CPC title

• G06F8/658

  Incremental updates; Differential updates · CPC title

• H04L63/1466

  Active attacks involving interception, injection, modification, spoofing of data unit addresses, e.g. hijacking, packet injection or TCP sequence number attacks · CPC title

• G06F21/57 Primary

  Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities · CPC title