Debug access of eyewear having multiple SoCs

Patent metadata

Field	Value
Publication number	US-12505058-B2
Application number	US-202318497034-A
Country	US
Kind code	B2
Filing date	Oct 30, 2023
Priority date	Dec 31, 2021
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

An eyewear device that includes a plurality of SoCs that share processing workload, and a USB port configured to perform low-power debugging and automation of the plurality of SoCs, such as using either a Universal Asynchronous Receiver-Transmitter (UART) or a Serial Wire Debug (SWD). The eyewear includes a USB hub configured such that the USB port can simultaneously communicate with the plurality of SoCs. The USB hub can be shut down to disable the USB hub, and all the SoCs can enter their low-power modes without being kept awake by a persistent USB connection. The eyewear includes a first switch and a control logic, wherein the control logic controls the first switch and enables the USB port to perform low-power debugging and automation of the SoCs. The eyewear further includes a second switch, wherein the control logic controls the second switch to enable the USB port to perform low-power debugging and automation of the SoCs via a processor, or to enable the USB port to control each of the SoCs.

First claim

What is claimed is:

1 . Eyewear, comprising:
a frame having a first side and a second side; a first system on a chip (SoC) adjacent the first side of the frame, the first SoC coupled to first electronic components; a second SoC adjacent the second side of the frame, the second SoC coupled to second electronic components; a universal serial bus (USB) port; a USB hub coupled to the USB port, wherein the USB hub is configured to enable a processor to control each of the first and second SoCs; and a switch configured to control the USB port to perform debugging and automation of the first and second SoCs.

2 . The eyewear of claim 1 , further comprising a processor coupled to the USB port and each of the first and second SoCs.

3 . The eyewear of claim 1 , wherein the USB hub is disabled when the USB port is configured to perform low-power debugging and automation of the first and second SoCs.

4 . The eyewear of claim 1 , wherein the USB port is configured to perform low-power debugging and automation using either a Universal Asynchronous Receiver-Transmitter (UART) or a Serial Wire Debug (SWD).

5 . The eyewear of claim 1 , further comprising control logic coupled to the switch, wherein the control logic is configured to control the switch and enable the USB port to perform low-power debugging and automation of the first and second SoCs via the processor.

6 . The eyewear of claim 5 , further comprising another switch, wherein the control logic is configured to control the other switch to enable the USB port to control each of the first and second SoCs.

7 . The eyewear of claim 5 , wherein the control logic is configured to disable the USB hub such that the first and second SoCs enter low-power modes without being kept awake by a persistent USB connection.

8 . The eyewear of claim 5 , further comprising a USB controller configured to provide a device test system (DTS) detection to the control logic to allow full recovery using the USB port.

9 . The eyewear of claim 5 , wherein the first SoC is configured to enable the control logic to control the switch and enable the USB port to perform low-power debugging and automation of the first and second SoCs via the processor.

10 . A method of using eyewear having a frame having a first side and a second side, a first system on a chip (SoC) adjacent the first side of the frame, the first SoC coupled to first electronic components, a second SoC adjacent the second side of the frame, the second SoC coupled to second electronic components, a universal serial bus (USB) port, a USB hub coupled to the USB port, wherein the USB hub is configured to enable a processor to control each of the first and second SoCs, a switch configured to control the USB port to perform debugging and automation of the first and second SoCs comprising:
configuring the USB port to control each of the first and second SoCs; and enabling the USB port to perform low-power debugging and automation of the first and second SoCs.

11 . The method of claim 10 , further comprising a processor coupled to the USB port and each of the first and second SoCs, the processor enabling the USB port to perform low-power debugging and automation of the first and second SoCs.

12 . The method of claim 10 , further comprising disabling the USB hub such that the USB port performs low-power debugging and automation of the first and second SoCs.

13 . The method of claim 10 , wherein the USB port performs low-power debugging and automation using either a Universal Asynchronous Receiver-Transmitter (UART) or a Serial Wire Debug (SWD).

14 . The method of claim 10 , wherein the eyewear further comprises control logic, wherein the control logic controls the switch and enables the USB port to perform low-power debugging and automation of the first and second SoCs via the processor.

15 . The method of claim 14 , wherein the eyewear further comprises another switch, wherein the control logic controls the other switch to enable the USB port to control each of the first and second SoCs.

16 . The method of claim 14 , wherein the control logic disables the USB hub such that the first and second SoCs enter low-power modes without being kept awake by a persistent USB connection.

17 . The method of claim 14 , wherein the eyewear further comprises a USB providing a device test system (DTS) detection to the control logic to allow full recovery using the USB port.

18 . The method of claim 14 , wherein the first SoC enables the control logic to control the switch and enable the USB port to perform low-power debugging and automation of the first and second SoCs via the processor.

19 . A non-transitory computer-readable medium storing program code which, when executed by a processor of eyewear having a frame having a first side and a second side, a first system on a chip (SoC) adjacent the first side of the frame, the first SoC coupled to first electronic components, a second SoC adjacent the second side of the frame, the second SoC coupled to second electronic components, a universal serial bus (USB) port, and a USB hub coupled to the USB port, is operative to cause a computing device to perform the steps of:
enabling the USB port to perform low-power debugging and automation of the first and second SoCs; and controlling a switch to enable the USB port to perform low-power debugging and automation of the first and second SoCs.

20 . The non-transitory computer-readable medium of claim 19 , wherein the code is operative to control another switch to enable the USB port to control each of the first and second SoCs.

Assignees

• Feinman Alex
• Heger Jason
• Moubedi Shaheen
• Nilles Gerald
• Recchio John
• Vadivelu Praveen Babu
• Snap Inc

Inventors

• Feinman Alex
• Heger Jason
• Moubedi Shaheen
• Nilles Gerald
• Recchio John
• Vadivelu Praveen Babu

Classifications

• G06F2213/0042

  Universal serial bus [USB] · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F1/163 Primary

  Wearable computers, e.g. on a belt · CPC title

• H04N13/239

  using two two-dimensional [2D] image sensors having a relative position equal to or related to the interocular distance (H04N13/243 takes precedence) · CPC title