Storage device based on flash memory and method for managing prefetch data thereof

Patent metadata

Field	Value
Publication number	US-12505044-B2
Application number	US-202418643160-A
Country	US
Kind code	B2
Filing date	Apr 23, 2024
Priority date	Oct 23, 2023
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Disclosed is a storage device. The storage device includes: a memory device; a buffer memory configured to store partial data among data stored in the memory device; and a memory controller configured to determine prefetch logical addresses expected to be received sequentially after sequential logical addresses are received from a host, to read prefetch data corresponding to the prefetch logical addresses from the memory device to store the prefetch data as a prefetch group of in the buffer memory, and to release the prefetch group from the buffer memory in response to a logical address discontinuous with the logical addresses being received from the host.

First claim

What is claimed is:

1 . A storage device comprising:
a memory device; a buffer memory configured to store partial data among data stored in the memory device; and a memory controller configured to determine prefetch logical addresses expected to be received sequentially after sequential logical addresses are received from a host, to read prefetch data corresponding to the prefetch logical addresses from the memory device, to store the prefetch data as a prefetch group of in the buffer memory, and to release the prefetch group from the buffer memory in response to a logical address discontinuous with the logical addresses being received from the host.

2 . The storage device of claim 1 , wherein the memory controller is configured to:
compare specified portion addresses among first logical addresses in response to the first logical addresses being received from the host, determine whether the first logical addresses are sequential based on the comparison, and set a prefetch cache in the buffer memory in response to the first logical addresses being sequential.

3 . The storage device of claim 2 , wherein the memory controller is configured to:
determine expected first prefetch logical addresses in response to the first logical addresses continuing to be received sequentially, and store first prefetch group data corresponding to the first prefetch logical addresses in the prefetch cache based on a size of the prefetch cache before the first prefetch logical addresses are received from the host.

4 . The storage device of claim 3 , wherein the memory controller is configured to release prefetch hit data among the first prefetch group data by single prefetch aborting.

5 . The storage device of claim 3 , wherein the memory controller is configured to release the first prefetch group data by mass prefetch aborting in response to second logical addresses which are discontinuous with the first logical addresses being received from the host.

6 . The storage device of claim 5 , wherein the memory controller is configured to:
determine whether the second logical addresses are sequential, determine expected second prefetch logical addresses in response to the second logical addresses continuing to be received sequentially and in response to the second logical addresses being sequential, and store second prefetch group data corresponding to the second prefetch logical addresses in the prefetch cache before the second prefetch logical addresses are received from the host.

7 . The storage device of claim 3 , wherein the memory controller is configured to store the first prefetch group data in the prefetch cache at a first speed and receive the first logical addresses at the first speed after a time determined based on the size of the prefetch cache.

8 . The storage device of claim 3 , wherein
the first prefetch group data includes first prefetch data and second prefetch data, the first prefetch data includes first user data, a first previous tag, and a first next tag, the second prefetch data includes second user data, a second previous tag, and a second next tag, and the memory controller is configured to match the first next tag and the second previous tag to connect the first prefetch data and the second prefetch data into one group.

9 . A prefetch management method of a storage device, the method comprising:
performing a first prefetch operation in response to receiving a first sequential workload from a host; boosting a speed of the first prefetch operation based on the first sequential workload; monitoring whether a prefetch hit occurs in first prefetch group data stored in a buffer memory by the first prefetch operation; releasing prefetch data in which the prefetch hit occurs among the first prefetch group data by single prefetch aborting; and releasing the first prefetch group data by mass prefetch aborting in response to receiving a second workload discontinuous with the first sequential workload from the host.

10 . The method of claim 9 , wherein the performing the first prefetch operation includes prefetching the first prefetch group data corresponding to the first sequential workload from a memory device to the buffer memory.

11 . The method of claim 9 , wherein the boosting the speed of the first prefetch operation includes storing the first prefetch group data corresponding to the first sequential workload in the buffer memory before the first sequential workload is received.

12 . The method of claim 9 , further comprising:
determining a time boosting the speed of the first prefetch operation based on a size of the buffer memory.

13 . The method of claim 9 , wherein the monitoring whether the prefetch hit occurs includes:
after a time determined based on a size of the buffer memory, storing the first prefetch group data in the buffer memory at a first speed; and receiving the first sequential workload at the first speed.

14 . The method of claim 9 , further comprising:
performing a second prefetch operation corresponding to the second workload in response to the second workload being sequential; and boosting a speed of the second prefetch operation based on the second workload.

15 . The method of claim 14 , further comprising:
maintaining the speed of the second prefetch operation to be same as a reception speed of the second workload after a time determined based on a size of the buffer memory.

16 . A storage device comprising:
a memory device; a buffer memory including a prefetch cache configured to store prefetch data corresponding to a workload received from a host; and a memory controller configured to read data corresponding to a sequential workload from the memory device and store the data in the prefetch cache in response to the sequential workload being received from the host, wherein the memory controller is configured to: perform a first prefetch operation corresponding to a first workload in response to a first sequential workload being received from the host; boost a speed of the first prefetch operation based on a size of the prefetch cache; and release all prefetch data prefetched by the first prefetch operation from the prefetch cache by mass prefetch aborting in response to a second workload discontinuous with the first workload being received from the host.

17 . The storage device of claim 16 , wherein the memory controller is configured to detect whether the first workload is sequential by comparing specified partial logical addresses included in the first workload in response to the first workload being received.

18 . The storage device of claim 16 , wherein the memory controller is configured to set the prefetch cache having a specified size within the buffer memory in response to the first workload being detected to be sequential.

19 . The storage device of claim 18 , wherein the memory controller is configured to maintain the speed of the first prefetch operation to be same as a reception speed of the first workload after a time determined based on the size of the prefetch cache.

20 . The storage device of claim 16 , wherein the memory controller is configured to release prefetch hit data among a first prefetch group data stored in the prefetch cache through the first prefetch operation by single prefetch aborting.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Kyungjune
• Kang Donggil
• Oh Minsik
• Kim Yoon Soo
• Kim Jongmin
• Um Kyungsik
• Jeong Myunggwan

Classifications

• G06F2212/6022

  Using a prefetch buffer or dedicated prefetch cache · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0656 Primary

  Data buffering arrangements · CPC title