Memory device and its operating method, memory system and operating method thereof

Patent metadata

Field	Value
Publication number	US-12505035-B2
Application number	US-202418595838-A
Country	US
Kind code	B2
Filing date	Mar 5, 2024
Priority date	Nov 6, 2023
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

An example of the present application discloses a memory device and operating method thereof, a memory system and operating method thereof, wherein the memory device includes: an array of memory cells; a peripheral circuit coupled to the array of memory cells and configured to: obtain a first result corresponding to a target location in the array of memory cells at an initial target read voltage; perform multiple adjustments to the initial target read voltage, and obtain the first result corresponding to the target location at the target read voltage after each of the adjustments respectively; determine a valley voltage in accordance with a plurality of the obtained first results.

First claim

What is claimed is:

1 . A memory device, comprising:
an array of memory cells; and a peripheral circuit coupled to the array of memory cells and configured to:
obtain a first result corresponding to a target location in the array of memory cells at an initial target read voltage; wherein the first result includes information which represents a number of bits at the target location which are flipped in a result of reading at a target read voltage relative to specified data which is actually stored; and wherein the specified data is stored at the target location;
perform multiple adjustments to the initial target read voltage, and obtain a first result corresponding to the target location at the target read voltage after each of the multiple adjustments respectively;
if a change from a failed state to at least one pass state and then to the failed state again is indicated by a plurality of the first results corresponding to target read voltages after multiple adjustments, stop adjusting the initial target read voltage; and
determine a valley voltage in accordance with a plurality of the obtained first results; wherein the valley voltage is a read voltage for performing a read operation on the array of memory cells.

2 . The memory device of claim 1 , wherein:
the array of memory cells includes a plurality of memory blocks, each of the memory blocks includes a plurality of memory rows, and each of the memory rows includes a plurality of memory cells; a preset number of the memory cells form a code word; the peripheral circuit is configured to:
in a process of performing a write operation on the array of memory cells, write the specified data at the target location in the array of memory cells; and
the target location includes at least one of each of the memory blocks, each of the memory rows, and each of the code words.

3 . The memory device of claim 1 , wherein the peripheral circuit is configured to:
store the specified data; read the specified data stored at the target location at the initial target read voltage to obtain a second result; perform a logical operation on the stored specified data and the second result to obtain a third result; when the first result includes the number of bits which represents the number of bits at the target location which are flipped in the result of reading at the target read voltage relative to specified data which is actually stored, count the number of bits in the third result that represent flip of bits in the second result relative to the specified data, and take the result of counting to be the first result; and when the first result includes information which represents a relationship of size between the number of bits at the target location which are flipped in a result of reading at the target read voltage relative to specified data which is actually stored and a first preset value, compare the number of bits in the third result that represent flip of bits in the second result relative to the specified data with a first preset value, and take the result of comparing to be the first result.

4 . The memory device of claim 3 , wherein the peripheral circuit comprises:
a first latch configured to store the specified data; a second latch configured to store the second result; and a third latch configured to store the third result.

5 . The memory device of claim 3 , wherein:
the first result includes information which represents a relationship of size between the number of bits at the target location which are flipped in a result of reading at the target read voltage relative to specified data which is actually stored and a first preset value; when the number of bits in the third result which represents the number of bits in the second result which are flipped relative to the specified data is greater than the first preset value, the first result is a failed state; and when the number of bits in the third result which represents the number of bits in the second result which are flipped relative to the specified data is less than or equal to the first preset value, the first result is a pass state.

6 . The memory device of claim 5 , wherein the peripheral circuit is configured to:
when multiple adjustments are performed to the initial target read voltage, perform a first adjustment to the initial target read voltage after a previous adjustment for each of the multiple adjustments, a step size of the first adjustment being a fixed value.

7 . The memory device of claim 6 , wherein the peripheral circuit is configured to:
when a number of pass states between failed states at two ends indicated by the plurality of first results corresponding to adjusted target read voltages include one, take an adjusted target read voltage corresponding to at least one pass state to be the valley voltage, wherein the at least one pass state comprises a plurality of pass states; and when the number of pass states between the failed states at two ends indicated by the plurality of first results corresponding to the adjusted target read voltages include more than one, take the adjusted target read voltage corresponding to one pass state at a middle position among the plurality of pass states to be the valley voltage.

8 . The memory device of claim 6 , wherein the peripheral circuit is configured to:
after a first pass state after failed states occurs among the plurality of first results corresponding to the target read voltages after multiple adjustments, perform a second adjustment to the read voltage after a previous adjustment, the step size of the second adjustment being less than that of the first adjustment.

9 . The memory device of claim 6 , wherein the peripheral circuit is configured to:
after a first pass state after failed states occurs among the plurality of first results corresponding to the target read voltages after multiple adjustments, perform a third adjustment to the read voltage after a previous adjustment in accordance with the result of counting in the third result corresponding to the first pass state, the step size of the third adjustment varying according to the number of bits in the third result which represents the number of bits in the second result which are flipped relative to the specified data.

10 . The memory device of claim 3 , wherein:
the first result includes the number of bits which represents the number of bits at the target location which are flipped in a result of reading at the target read voltage relative to specified data which is actually stored; the peripheral circuit is configured to:
when the first result corresponding to the initial target read voltage is less than or equal to the first preset value, perform a first adjustment to the initial target read voltage in accordance with the first result to obtain a target adjusted read voltage; and
obtain a first result corresponding to the target location at the target adjusted read voltage.

11 . The memory device of claim 10 , wherein the peripheral circuit is configured to:
when the first result corresponding to the target location at the target adjusted read voltage is less than the first preset value and greater than a second preset value, continue to perform the first adjustment to the target adjusted read voltage, and obtain a first result corresponding to the target location at the adjusted read voltage, until the first result corresponding to a final adjusted read voltage is less than or equal to the second preset value, a step size of the first adjustment varying in accordance with a value of the first result; and when the first result corresponding to the final adjusted read voltage is less than or equal to the second

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Tang Xingwei
• Ye Guangchang
• Guo Lu

Classifications

• G06F2212/7208

  Multiple device management, e.g. distributing data over multiple flash devices · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title