Self-optimizing corrective read offsets with lateral charge migration proxies

Patent metadata

Field	Value
Publication number	US-12504886-B2
Application number	US-202418407366-A
Country	US
Kind code	B2
Filing date	Jan 8, 2024
Priority date	Jan 11, 2023
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

A memory sub-system with a memory device having a plurality of cells, and the plurality of cells having a set of cells, and a processing device operatively coupled to the memory device, the processing device to perform operations of determining a level information associated with the set of cells, where the set of cells comprise a target cell associated with a read operation, identifying a read level offset for the target cell based on the level information, and performing the read operation in accordance with the read level offset.

First claim

What is claimed is:

1 . A memory sub-system comprising:
a memory device comprising a plurality of cells, the plurality of cells comprising a set of cells; and a processing device operatively coupled to the memory device, the processing device to perform operations comprising:
determining a level information associated with the set of cells, wherein the set of cells comprises a target cell associated with a read operation;
identifying a read level offset for the target cell based on the level information; and
performing the read operation in accordance with the read level offset.

2 . The memory sub-system of claim 1 , wherein the level information comprises a level state-width, and wherein the level information is associated with a lowest programmable level of the set of cells.

3 . The memory sub-system of claim 2 , the operations further comprising:
issuing a first strobe to the lowest programmable level; determining, based on the first strobe, a first failed bit count of the lowest programmable level; issuing a second strobe to the lowest programmable level; determining, based on the second strobe, a second failed bit count of the lowest programmable level; and determining the level state-width based on the first failed bit count and the second failed bit count.

4 . The memory sub-system of claim 1 , wherein to identify the read level offset, the operations further comprise:
identifying a read operation type; identifying a set of trims associated with the read operation type; and identifying one or more trims associated with the level information from the set of trims, wherein the read level offset comprises the one or more trims.

5 . The memory sub-system of claim 4 , wherein the read operation type is a corrective read operation.

6 . The memory sub-system of claim 1 , wherein the level information comprises a level shift, and wherein the level information is associated with a highest programmable level of the set of cells.

7 . The memory sub-system of claim 6 , the operations further comprising:
identifying a program/erase (P/E) cycle count associated with a wordline group corresponding to the set of cells; identifying the level shift associated with the highest programmable level; and identifying the read level offset based on the level shift, the P/E cycle count, and the wordline group.

8 . A method comprising:
determining, by a processing device, a level information of a set of cells, wherein the set of cells comprises a target cell associated with a read operation; identifying a read level offset for the target cell based on the level information; and performing the read operation in accordance with the read level offset.

9 . The method of claim 8 , wherein the level information comprises a level state-width, and wherein the level information is associated with a lowest programmable level of the set of cells.

10 . The method of claim 9 , further comprising:
issuing a first strobe to the lowest programmable level; determining, based on the first strobe, a first failed bit count of the lowest programmable level; issuing a second strobe to the lowest programmable level; determining, based on the second strobe, a second failed bit count of the lowest programmable level; and determining the level state-width based on the first failed bit count and the second failed bit count.

11 . The method of claim 8 , further comprising:
identifying a read operation type; identifying a set of trims associated with the read operation type; and identifying one or more trims associated with the level information from the set of trims, wherein the read level offset comprises the one or more trims.

12 . The method of claim 11 , wherein the read operation type is a corrective read operation.

13 . The method of claim 8 , wherein the level information comprises a level shift, and wherein the level information is associated with a highest programmable level of the set of cells.

14 . The method of claim 13 , wherein to determine the level information, the method further comprises:
identifying a program/erase (P/E) cycle count associated with a wordline group corresponding to the set of cells; identifying the level shift associated with the highest programmable level; and identifying the read level offset based on the level shift, the P/E cycle count, and the wordline group.

15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
receiving, by the processing device, a read request to perform a read operation on a target cell of a set of cells of a plurality of cells of a memory device; determining a level information of the set of cells; identifying a read level offset for the target cell based on the level information; and responsive to identifying the read level offset, performing the read operation in accordance with the read level offset.

16 . The non-transitory computer-readable storage medium of claim 15 , wherein the level information comprises a level state-width, and wherein the level information is associated with a lowest programmable level of the set of cells.

17 . The non-transitory computer-readable storage medium of claim 16 , the operations further comprising:
issuing a first strobe to the lowest programmable level; determining, based on the first strobe, a first failed bit count of the lowest programmable level; issuing a second strobe to the lowest programmable level; determining, based on the second strobe, a second failed bit count of the lowest programmable level; and determining the level state-width based on the first failed bit count and the second failed bit count.

18 . The non-transitory computer-readable storage medium of claim 15 , the operations further comprising:
identifying a read operation type; identifying a set of trims associated with the read operation type; and identifying one or more trims associated with the level information from the set of trims, wherein the read level offset comprises the one or more trims.

19 . The non-transitory computer-readable storage medium of claim 15 , wherein the level information comprises a level shift, and wherein the level information is associated with a highest programmable level of the set of cells.

20 . The non-transitory computer-readable storage medium of claim 19 , the operations further comprising:
identifying a program/erase (P/E) cycle count associated with a wordline group corresponding to the set of cells; identifying the level shift associated with the highest programmable level; and identifying the read level offset based on the level shift, the P/E cycle count, and the wordline group.

Assignees

• Micron Technology Inc

Inventors

• Nicosia Gianluca
• Goda Akira
• Righetti Niccolo

Classifications

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C2029/5004

  Voltage · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title