Mechanism for saving power on a bus interface

Patent metadata

Field	Value
Publication number	US-12504806-B2
Application number	US-202318337189-A
Country	US
Kind code	B2
Filing date	Jun 19, 2023
Priority date	Jul 31, 2020
Publication date	Dec 23, 2025
Grant date	Dec 23, 2025

Abstract

Systems, apparatuses, and methods for saving power on a bus interface are described. A system includes a host, a device, and a repeater interposed between the host and the device. While the host and device are in a low-power state, the repeater monitors a first bus to determine if the device has woken up. When the repeater detects a remote wake-up event initiated by the device, the repeater generates an interrupt which is sent to the host. The host responds to the interrupt by initiating a resume wake-up event procedure that assumes the device is still asleep. In this way, the host is able to stay in the low-power state longer while also using a wake-up procedure that does not require the host to be aware of the existence of the repeater.

First claim

What is claimed is:

1 . An apparatus, comprising:
a repeater interposed between a host and a device connected via a bus, wherein the host and the device respectively implement a communications protocol over the bus, wherein the bus comprises a first portion connecting the host to the repeater and a second portion connecting the repeater and the device, and wherein the repeater is configured to:
detect a first type of wake-up event on the bus signaled via the communications protocol from the device over the second portion of the bus, while for the first portion of the bus is in a low-power state; and
convert the first type of wake-up event to a second type to signal the wake-up event to the host using a sideband path separate from the bus.

2 . The apparatus as recited in claim 1 , wherein at least the first portion of the bus is in compliance with a universal serial bus (USB), and wherein the communications protocol is in compliance with a USB protocol.

3 . The apparatus as recited in claim 1 , wherein the host is located on a first integrated circuit (IC), and wherein the repeater is located on a second IC.

4 . The apparatus as recited in claim 1 , wherein to signal the wake-up event the repeater is further configured to trigger an interrupt on the host using the sideband path.

5 . The apparatus as recited in claim 1 , wherein the wake-up event on the bus is a voltage transition generated by the device.

6 . The apparatus as recited in claim 1 , wherein the host connects to the bus via a host interface, and wherein the low-power state of the first portion of the bus comprises the host interface being placed in one of a power-gated state and a clock-gated state.

7 . The apparatus as recited in claim 6 , wherein the first portion of the bus conveys signals at a first voltage level, wherein the second portion of the bus conveys signals at a second voltage level, and wherein the first voltage level is less than the second voltage level.

8 . A method utilizing a repeater interposed on a bus between a host and a device, the method comprising performing by the repeater:
detecting a first type of wake-up event on the bus signaled via the communications protocol from the device, while the communications protocol is disabled at the host, wherein the host and the device respectively implement the communications protocol over the bus, and wherein the repeater implements at least a portion of the communications protocol with the device; and converting the first type of wake-up event to a second type to signal the host using a sideband path separate from the bus.

9 . The method as recited in claim 8 , wherein the bus is in compliance with a universal serial bus (USB), and wherein the communications protocol is in compliance with a USB protocol.

10 . The method as recited in claim 8 , wherein the host is located on a first integrated circuit (IC), and wherein the repeater is located on a second IC.

11 . The method as recited in claim 8 , wherein the repeater is further configured to signal the wake-up event by triggering an interrupt on the host.

12 . The method as recited in claim 8 , wherein the wake-up event on the bus is a voltage transition generated by the device.

13 . The method as recited in claim 8 , wherein the host connects to the bus via a host interface, wherein the communications protocol is disabled at the host due to the host interface being in one of a power-gated state and a clock-gated state.

14 . The method as recited in claim 13 , wherein the repeater is configured to convey signals to the device at a first voltage level, wherein the repeater is configured to convey signals to the host interface at a second voltage level, and wherein the first voltage level is greater than the second voltage level.

15 . A system comprising:
a host connected to a first bus and configured to implement a communications protocol over the first bus, wherein the host comprises a sideband signal different from the first bus; a device connected to a second bus and configured to implement the communications protocol over the second bus; and a repeater connected to the first bus and the second bus, the repeater configured to:
implement at least a portion of the communications protocol with the device;
detect a first type of wake-up event on the second bus signaled via the communications protocol while the first bus is in a sleep state, and
responsive to the wake-up event:
convert the first type of wake-up event to a second type to signal the host using the sideband signal.

16 . The system as recited in claim 15 , wherein the first bus and the second bus are in compliance with a universal serial bus (USB), and wherein the communications protocol is in compliance with a USB protocol.

17 . The system as recited in claim 15 , wherein the host is located on a first integrated circuit (IC), and wherein the repeater is located on a second IC.

18 . The system as recited in claim 15 , wherein to signal the wake-up event the repeater is further configured to trigger an interrupt on the host via the sideband signal.

19 . The system as recited in claim 15 , wherein the host is connected to the first bus via a host interface, and wherein the sleep state of the first bus comprises the host interface being in one of a power-gated state and a clock-gated state.

20 . The system as recited in claim 15 , wherein the first bus comprises a first voltage level, wherein the second bus comprises a second voltage level, and wherein the first voltage level is less than the second voltage level.

Assignees

• Apple Inc

Inventors

• Franko Itay
• Iwamoto Derek
• Damarillo Mark Ferdinand
• Ferry William O
• Chen Yi-Chun

Classifications

• G06F1/3209

  Monitoring remote activity, e.g. over telephone lines or network connections · CPC title

• G06F11/3027

  where the computing system component is a bus · CPC title

• G06F11/3062

  where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title

• H04B3/36 Primary

  Repeater circuits (H04B3/58 takes precedence) · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title